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[Other] dsu_test

Description: hdlc程序,对要求实现FPGA对HDLC的控制.-"procedures, requirements for FPGA HDLC control.
Platform: | Size: 3091 | Author: zhx | Hits:

[Other] dsu_test

Description: hdlc程序,对要求实现FPGA对HDLC的控制.-"procedures, requirements for FPGA HDLC control.
Platform: | Size: 3072 | Author: zhx | Hits:

[VHDL-FPGA-Verilog] hdlc

Description: HDLC通信模块发送接收模块VHDL源码-HDLC communication module to send receiver module VHDL source code
Platform: | Size: 3072 | Author: ditto | Hits:

[VHDL-FPGA-Verilog] rece_7E

Description: HDLC控制接收数据开始标志7E和去零模块，用于FPGA与E1相接，Verilog HDL语言编写-HDLC control began to receive data to the zero mark 7E and modules for use in FPGA and E1 phase, Verilog HDL language
Platform: | Size: 2048 | Author: 刘彻 | Hits:

[VHDL-FPGA-Verilog] FPGAforDLC

Description: 采用Altera公司的FPGA芯片，在MAX+plus II软件平台上实现多路HDLC电路-Using Altera s FPGA chips, in MAX+ Plus II software platform to achieve multi-channel HDLC circuit
Platform: | Size: 62464 | Author: yangj2 | Hits:

[VHDL-FPGA-Verilog] trunk-hdlc

Description: 高级链路层协议的实现，vhdl，fpga-- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern is assumed only after the end of a frame which is signaled by an abort signal - Zero insertion - Abort pattern generation and checking - Address insertion and detection by software - CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used) - FIFO buffers and synchronization (External) - Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted) - Q.921, LAPB and LAPD compliant. - For complete specifications refer to spec document
Platform: | Size: 188416 | Author: | Hits:

[VHDL-FPGA-Verilog] hdlc

Description: 基于FPGA的HDLC协议控制器，能完成插零，删除0操作。-HDLC controller base on FPGA
Platform: | Size: 197632 | Author: | Hits:

[VHDL-FPGA-Verilog] hdlc

Description: HDLC接口协议的FPGA实现使用verilog-design of HDLC
Platform: | Size: 3697664 | Author: hanjinchao | Hits:

[Com Port] HDLC_VHDL

Description: 用VHDL实现从以太网到并行数据以及从并行数据到以太网的HDLC成帧解帧.附详细代码说明,方便阅读.可方面移植到Altera及Xilinx等厂家芯片,是做基于FPGA的以太网设计的好资料-Achieved using VHDL and parallel data from the Ethernet to parallel data from the HDLC framing solution to Ethernet frames. Attached detailed code instructions, easy to read. Can be ported to Altera and Xilinx areas such as chip manufacturers are doing to FPGA-based very good information network design
Platform: | Size: 11264 | Author: 卓福洲 | Hits:

[VHDL-FPGA-Verilog] hdlc

Description: HDLC协议控制器，用FPGA实现的verilog源代码-HDLC protocol controller, implemented with FPGA verilog source code
Platform: | Size: 1866752 | Author: 杜征宇 | Hits:

[VHDL-FPGA-Verilog] hdlc_latest[1]

Description: HDLC解码控制，包括CRC校验，可以在一片3400A FPGA上实现8解码-HDLC decoding control, including the CRC check can be realized in a 3400A FPGA 8 decoding
Platform: | Size: 573440 | Author: 宋珂 | Hits:

[VHDL-FPGA-Verilog] FPGA-HDLC-design

Description: 基于FPGA的HDLC协议控制器的设计。FPGA-based HDLC protocol controller design. Pdf-FPGA-based HDLC protocol controller design. Pdf
Platform: | Size: 1596416 | Author: iriu | Hits:

[VHDL-FPGA-Verilog] dddddddHDLC

Description: FPGA的入门级资料 讲的很好 不错 hdlc的实现-fpga
Platform: | Size: 2253824 | Author: wangyang | Hits:

[VHDL-FPGA-Verilog] HDLC

Description: verilog HDL语言编写的HDLC协议的IP核，包括通讯控制及CRC。-written in verilog HDL HDLC protocol IP core, including communications control and CRC.
Platform: | Size: 69632 | Author: 王强 | Hits:

[VHDL-FPGA-Verilog] hdlc

Description: 基于FPGA的hdlc协议控制器的实现，用vhdl语言编写。-FPGA-based implementation of hdlc protocol controller, using vhdl language.
Platform: | Size: 6144 | Author: zizi | Hits:

[Documents] HDLC的FPGA实现方法.rar

Description: 介绍了HDLC的FPGA实现方法，介绍了HDLC的FPGA实现方法
Platform: | Size: 819135 | Author: 2594357508@qq.com | Hits:

[VHDL-FPGA-Verilog] hdlc

Description: HDLC通信协议，FPGA实现，包含源文件和仿真测试文件。-HDLC comunication
Platform: | Size: 355328 | Author: lirui | Hits:

[Picture Viewer] HDLC-code

Description: 网络通信的HDLC源码，使用CPLD/FPGA实现-HDLC network communications source code, the use of CPLD/FPGA to achieve
Platform: | Size: 65536 | Author: albert | Hits:

[VHDL-FPGA-Verilog] HDLC_FPGA

Description: HDLC接口协议的FPGA实现,使用Verilog hdl-FPGA HDLC interface protocol implementation using Verilog hdl
Platform: | Size: 3698688 | Author: 海大王 | Hits:

[Program doc] HDLC-protocol-RS485

Description: Paper: in HDLC protocol RS485 bus controller of the FPGA implementation
Platform: | Size: 429056 | Author: 宁一寒 | Hits:
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