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[SCM] dds

Description: 关于FPGA中DDS核参数设置的资料，英文版的XILINX资料-DDS on the FPGA in the data set of nuclear parameters, the English version of XILINX information
Platform: | Size: 1664000 | Author: 李晶 | Hits:

[VHDL-FPGA-Verilog] dds_easy

Description: 直接频率合成DDS模块的ise工程，可以直接下载，在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波，也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位，可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram，为节省储存空间仅需要储存1/4周期的数据。根据需要，可以重新修改数据，改变波形。-DDS direct frequency synthesizer module ，ise project, can be directly downloaded through the Spartan3/Spartan3E and tested successfully. The DDS module can generate two-channel sine wave of different frequency, or produce the same frequency arbitrary waveform phase difference of the phase shift. There is a 32-bit accumulator to generate 12 bit phase-precision 12-bit quantization precision of the sine wave. Cases the design of a Block Ram, in order to save storage space need to store only 1/4 cycle of data. Necessary, can modify data, change the waveform.
Platform: | Size: 471040 | Author: 郭先生 | Hits:

[VHDL-FPGA-Verilog] CORDIC_SINE

Description: xilinx的ISE工程，用CORDIC算法做DDS生成正弦波-xilinx the ISE project to do with the CORDIC algorithm generates sine DDS
Platform: | Size: 14447616 | Author: 刘伟 | Hits:

[VHDL-FPGA-Verilog] 5-15

Description: DDS的实现，在XILINX的FPGA验证通过。使用ROM实现的。-DDS implementations, in XILINX FPGA verification by. Using ROM.
Platform: | Size: 8192 | Author: wh | Hits:

[VHDL-FPGA-Verilog] Codes-and-Reports

Description: Verilog Source code for arbitrary waveform generator- simple DDS algorithm codes run on Xilinx Spartan-3E fpga to show output on dac pin. Please see the included report. its really simple to implement. all source code is given.
Platform: | Size: 10629120 | Author: imranity | Hits:

[Other] DDS

Description: 附件包括1.基于FPGA实现DDS正弦波产生2.对应程设计说明一份3.重要说明一份。使用的软件平台为ISE13.3，硬件平台为Xilinx公司的V4板子。-DDS generator
Platform: | Size: 5718016 | Author: zhulinglei | Hits:

[VHDL-FPGA-Verilog] ZHWX

Description: DDS 产生正弦信号，OOK，AM三种波形。 使用xilinx FPGA VHDL-DDS. Resulting in sinusoidal signal, OOK, AM three waveforms. Using xilinx FPGA VHDL.
Platform: | Size: 2836480 | Author: 张文轩 | Hits:

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