Description: 有实验结果,用MOSIN6编写的,是Verilog HDL语言实现的.
练习三 利用条件语句实现计数分频时序电路
实验目的：
1. 掌握条件语句在简单时序模块设计中的使用；
2. 学习在Verilog模块中应用计数器；
3. 学习测试模块的编写、综合和不同层次的仿真。
练习四 阻塞赋值与非阻塞赋值的区别
实验目的：
1． 通过实验，掌握阻塞赋值与非阻塞赋值的概念和区别；
2． 了解阻塞赋值与非阻塞赋值的不同使用场合；
3． 学习测试模块的编写、综合和不同层次的仿真。
-The experimental results are used to prepare MOSIN6 is achieved Verilog HDL language. Practice the use of conditional statements to achieve the three sub-frequency timing circuit count experimental purposes: 1. Have conditional statements in the simple timing of the use of modular design 2. Learning modules in the Verilog Application of counter 3. to learn the preparation of the test module, integrated and different levels of simulation. Practicing the four blocking assignment with the distinction between non-blocking assignment experimental purposes: 1. Through experiments, hands blocking assignment with the concept of non-blocking assignment and distinction 2. Understanding of blocking and nonblocking assignment assignment using different occasions 3. Test the preparation of learning modules, integrated and different levels of simulation. Platform: |
Size: 15360 |
Author:盼盼 |
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Description: 利用QuartusII的"MegaWizard Plug-In Manager",
设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE
把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行
时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。
2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_COUNTER，
设计一个20bit的up_only COUNTER,
要求该COUNTER在FE0FA和FFFFF之间自动循环计数；
分析该COUNTER在EPM7128SLC84-7、EPM7128SLC84-10、和EPF10K70RC240-2、
EPF10K70RC240-4几种芯片中的最大工作频率；
请将计数器的输出值在FFFFC--FE0FF之间的仿真波形打印出来
（仅EPF10K70RC240-4芯片,最大允许Clock频率下）。-QuartusII use the MegaWizard Plug-In Manager , the design of the input data width is 4bit the ADD, SUB, MULT, DIVIDE, COMPARE them as a project, DEVICE selected EPF10K70RC240-4, on their timing simulation, the simulation waveform (input output selected group) in a paper print out. 2. QuartusII use the MegaWizard Plug-In Manager in LPM_COUNTER, the design of a 20bit of up_only COUNTER, requested that the COUNTER in FE0FA and automatic cycle count between FFFFF analysis of the COUNTER in EPM7128SLC84-7, EPM7128SLC84-10, and EPF10K70RC240-2, EPF10K70RC240-4 Several of the largest chip operating frequency I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximum allowable Clock frequency). Platform: |
Size: 31744 |
Author:李侠 |
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Description: Abstract循序电路第一个应用是拿来做计数器((笔记) 如何设计计数器? (SOC) (Verilog) (MegaCore))，有了计数器的基础后，就可以拿计数器来设计除频器，最后希望能做出能除N的万用除频器。-Abstract The first application of sequential circuits are used to make counter ((notes) How to design a counter? (SOC) (Verilog) (MegaCore)), with the basic counter, you can use to design counters in addition to frequency, the last hope can make in addition to ten thousand with the exception of the N frequency. Platform: |
Size: 39936 |
Author:王媛媛 |
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Description: Verilog 编写的频率计，使用8位LED作为显示，Quartus II 6.0的工程文件。保证好用，EPM240T的芯片。使用了66 的资源。-Written in Verilog frequency counter, using 8-bit LED as the display, Quartus II 6.0 of the project file. To ensure easy to use, EPM240T chips. 66 of the resources used. Platform: |
Size: 585728 |
Author:石头 |
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Description: Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File.
The Pinout is descripted in the Constrained file quad.ucf.
To use them, you need teh XC9536 and a clock source that s 4 times faster than the fastes signal that the incremental encoder can creates. IThe clock source frequency is uncritical. For manuel rotated incremental encoder like radio VFO oder other tuning knob, a simple TTL oscillator with about 1Mhz (i use 1.8432Mhz and tested 32768Khz) works brilliant.
For very fast decoding, this core is not good enought because there are no Filter FlipFlops are programmed to suppress noises on the Channel A/B Lines.-Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File.
The Pinout is descripted in the Constrained file quad.ucf.
To use them, you need teh XC9536 and a clock source that s 4 times faster than the fastes signal that the incremental encoder can creates. IThe clock source frequency is uncritical. For manuel rotated incremental encoder like radio VFO oder other tuning knob, a simple TTL oscillator with about 1Mhz (i use 1.8432Mhz and tested 32768Khz) works brilliant.
For very fast decoding, this core is not good enought because there are no Filter FlipFlops are programmed to suppress noises on the Channel A/B Lines. Platform: |
Size: 70656 |
Author:JUPP |
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Description: 用verilog写的计数器，可用于分频等多种功能。已经调试成功很好用-Written with verilog counter, can be used for frequency and other functions. Has been very good success with debugging Platform: |
Size: 2048 |
Author:tangxiaolei |
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Description: EDA，verilog 语言写的频率计，一个是测频，一个是产生一定的频率作为信号源，可在cycloneII 上验证，-EDA, verilog language written in frequency counter, one frequency measurement, one is a certain frequency as the signal source can be verified on the cycloneII, thank you! ! Platform: |
Size: 652288 |
Author:谷向前 |
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Description: 这是用verilog写的配合DE2 FPGA开发板的10进制显示频率计的工程文件夹的压缩包，解压后可直接下载到DE2板上，其中频率输入端是系统自带27M时钟D13用于测试，如果想要应用于别的开发板，可以重新分配引脚。-DE2 FPGA development board with with verilog write with decimal display frequency meter project folder compression package, after decompression can be directly downloaded to the DE2 board, in which the frequency of the input of the system comes with 27M clock D13 used for testing If you want to apply to other development board can reassign pin. Platform: |
Size: 615424 |
Author:予烨 |
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Description: 用verilog实现的一个频率计数器，可分别在不同的频率下计数（自己设定），里面有几个有用的小模块，分频，计数，显示，同步，进位等-Verilog to achieve a frequency counter, respectively, in different frequency count (set), there are several useful modules, divide, count, display, synchronization, binary, etc. Platform: |
Size: 88064 |
Author:曾俊 |
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Description: verilog写的频率计 ，在数码管上显示10进制输入数字信号的频率。已在DEII上验证-
verilog write frequency counter, decimal display frequency of the input digital signal in the digital tube. Verified on DEII Platform: |
Size: 272384 |
Author:孔沛瑶 |
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Description: 利用Verilog设计的在停车场情况下的模拟的分频器和计数器的代码-The use of Verilog design in the parking lot in case of analog frequency divider and counter code Platform: |
Size: 10240 |
Author:陆晓忆 |
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Search - Frequency Counter in Verilog