Description: VHDL语言写的频率计的程序,内带完整的技术报告-VHDL write the frequency of procedures, brought integrity of the technical report Platform: |
Size: 317440 |
Author:刘西圣 |
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Description: 利用VHDL语言写的0到100MHZ频率计,只通过仿真,未在实验台验证,仅供参考-VHDL language using the 0 to 100MHz frequency counter, only through simulation, not in the test-bed validation, for reference only Platform: |
Size: 2048 |
Author:zengfan155 |
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Description: 以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计,采用在一定时间内对数字脉冲计数的方法,可直接测量TTL电平的数字脉冲信号的频率、周期和脉宽。其他一些信号可经过信号预处理电路变换后测量。
量程:1Hz~999999Hz
输入信号:(1)TTL电平数字脉冲信号;(2)方波/正弦波,幅度0.5~5V
显示:七段数码管显示频率(Hz)和周期/脉宽(us)
控制:两个拨码开关切换三种工作模式:测频率,测周期,测脉宽-Frequency Counter realized with Altera EPM7128SLC84-15. It can measure frequecy, cycle and pulse width of TTL sigals. Platform: |
Size: 1053696 |
Author:tom |
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Description: a simple implementation of a frequency meter with
the BCD-counter and the 7-segment LED display Platform: |
Size: 12288 |
Author:wangfeng |
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Description: 在电子技术中,频率是最基本的参数之一,又与许多电参量的测量方案、测量结果都有十分密切的关系,因此频率的测量就显得更为重要。测量频率的方法有多种,其中电子计数器测量频率具有精度高、使用方便、测量迅速,以及便于实现测量过程自动化等优点,是频率测量的重要手段之一。在本次毕业设计中我们选择使用单片机来制作数字频率计,并在实际制作中采用了直接测频法。利用延时产生的时基门控信号来控制闸门,通过在单位时间内计数器记录下的脉冲个数计算出输入信号的频率,最终送入LCD中显示。这样制作出来的频率计不仅可以满足设计题目的参数要求,而且具有了单片机的稳定性和成熟性,且控制能力强,是一种低成本,高可靠的设计方案。-In electronic technology, the frequency is one of the most basic parameters, but also with a number of electrical parameters of the measurement program, the measurement results have a very close relationship between the frequency of measurement, therefore it is even more important. Measurement of the frequency of a number of means, electronic measurement of the frequency counter with high precision, easy to use, rapid measurement, and measurement is easy to realize the advantages of process automation is an important means of measuring the frequency of one. Graduates in this design we have chosen to make use of single-chip digital frequency meter, and used in the actual production of a direct frequency measurement method. Delay arising from the use of gated time-base signal to control the gate time in units of the pulse counter to record the number of calculated frequency of the input signal, and ultimately into the LCD display. This produced not only the frequency of the parameters to Platform: |
Size: 220160 |
Author:张林锋 |
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Description: 用VHDL语言实现的计时器,最大计时为24小时,计时精度为1ms,设有复位和暂停功能,使用的晶振频率为50Hz。-VHDL language implementation of the timer with a maximum time of 24 hours, timing accuracy of 1ms, with reset, and pause functions, using the crystal oscillator frequency is 50Hz. Platform: |
Size: 3072 |
Author:周峰 |
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Description: 用vhdl实现频率计,提出一种用vhdl实现的等精度测频率系统设计。-Frequency counter using vhdl implementation is presented using vhdl achieve precision measurements such as frequency of system design. Platform: |
Size: 103424 |
Author:salanchen |
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Description: 当年本科时的毕业设计,信号发生器和频率计-The time of the year undergraduate graduate design, signal generator and frequency counter Platform: |
Size: 10240 |
Author:zhanglei |
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Description: 一个简单大家容易看的懂的频率计设计程序,可以实现自动换挡功能。-A simple and easy to see to understand all of the frequency counter design program that can automatically shift feature. Platform: |
Size: 2048 |
Author:zhangliang |
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Description: 基于FPGA的数字电子钟设计,系统总程序由分频模块、“时分秒”计数器模块、数据选择模块、报时模块、动态扫描显示和译码模块组成。得到一个将“时”、“分”、“秒”显示于人的视觉器官的计时装置。它的计时周期为24小时,显示满刻度为23时59分59秒,另外有校时、校分和整点报时功能,并通过数码管驱动电路显示计时结果。-FPGA-based design of digital electronic clock, the system program by the total frequency module, " the minutes and seconds" counter module, data selection module, timer module, dynamic scanning display and decoding module. Get a will " ," and " division" and " seconds" display on the human visual organ of the timing device. It' s time for the 24-hour period, indicating full scale as 23:59:59, and another school, the school hours and the whole hour, and through digital tube display driver circuit timing results. Platform: |
Size: 63488 |
Author:sunnan |
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Description: bcd十进制计数器,用于频率计设计的计数器单元,输出zeros用于选通量程使用!-bcd decimal counter, the counter for frequency counter design unit, the output zeros for the use of strobe range! Platform: |
Size: 1024 |
Author:jim |
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Description: 四位10进制VHDL频率计设计说明
四位频率计的结构包括一个测频率控制信号发生器、四个十进制计数器和一个十六位锁存器(本例中所测频率超过测频范围时有警示灯)。-Four 10-digit frequency counter VHDL design description of the structure of the four frequency meter includes a measuring frequency control signal generator, four decimal counter and a sixteen bit latch (in this case the measured frequency over a frequency measurement range warning lights). Platform: |
Size: 54272 |
Author:韦昊斯 |
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Description: 基于FPGA的频率计设计。通过FPGA运用、 HDL编程,利用FPGA(现场可编程门阵列)芯片设计了一个8位数字式等精度频率计,该频率计的测量范围为0-100MHZ,利用QUARTUS II集成开发环境进行编辑、综合、波形仿真,并下载到CPLD器件中,经实际电路测试,仿真和实验结果表明,该频率计有较高的实用性和可靠性。-Frequency counter FPGA-based design. By using FPGA, VHDL programming, the use of FPGA (field programmable gate array) chip design an 8-bit digital precision frequency meter, etc., the frequency meter measurement range of 0-100MHZ, using QUARTUS II integrated development environment for editing, synthesis, simulation waveforms, and downloaded to the CPLD device, the actual circuit testing, simulation and experimental results show that the frequency counter has a higher availability and reliability. Platform: |
Size: 595968 |
Author:吴亮 |
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Description: 这是使用VHDL语言编写的频率计数器源码。包含了各个模块以及主函数。-This is the source of the frequency counter using VHDL language. Contains various modules and the main function. Platform: |
Size: 1024 |
Author:张鑫 |
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