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[Other resource] 数字锁相环设计源程序

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF
Platform: | Size: 121399 | Author: 杰轩 | Hits:

[Other resource] [eda]vhdl

Description: 福州大学EDA选修课所有实验课程代码。VHDL语言描述（vhd），以及电路图（gdf）-Fuzhou University EDA optional courses in all experimental code. VHDL description (vhd), and circuit (GdF)
Platform: | Size: 222534 | Author: 林锋杰 | Hits:

[Other] v0.8b

Description: GE数据转换器ggfgfd gdf gdf-data converters ggfgfdgfdgdfgdfgdfgdfgdf
Platform: | Size: 63900 | Author: guase | Hits:

[Other] vhdl

Description: 基于MAXPLUS II 的软件设计，这里面有几个小程序，用于VHDL的GDF设计，含有LED数码管的显示驱动程序，还有3选一，十选一程序。-II FPGA-based design software, there are several small procedures, GDF for VHDL design with a digital LED display driver of the procedures, there is a three elections. 10 election procedure.
Platform: | Size: 2442 | Author: 梁兵 | Hits:

[Other resource] BASED_FLEX10k20_cymometer

Description: 基于FLEX10K的频率计设计，采用分层设计，顶层文件为GDF，其余为VHDL代码，有一定的参考价值。
Platform: | Size: 208423 | Author: 谭涌 | Hits:

[Other resource] gdf

Description: 　根据城市交通路网建设的实际, 研究了描述城市交通网络图的城市道路数据库的组织结构, 在此数据结构的基础上依靠G IS 技术的支持, 采集了大量具体道路信息, 采用D ijk st ra 算法实现了快速最短路径搜索。根据城市的交通状况对交通网络图的边值赋予不同的权值可实现最优路径搜寻, 给出了一个搜索实例——一个包含61 个交通路口的最短路径搜索结果的搜索时间约为1. 1
Platform: | Size: 183097 | Author: 王功臣 | Hits:

[Other resource] simulation_aufgabe1

Description: MATLAB 在数学建模中的应用 LDF,GDF,FDF错误的算法
Platform: | Size: 2748 | Author: 李贵 | Hits:

[GDI-Bitmap] GDFViewer

Description: 识别GDF地图文件，画图程序，能够实现对地图文件的基本操作,如移动、放大、缩小、鼠标点击拖动、鼠标点击缩放、动态选择地图层（layer）绘图等。
Platform: | Size: 50396 | Author: ankeer | Hits:

[Other resource] 数字锁相环

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
Platform: | Size: 125197 | Author: 于洪彪 | Hits:

[VHDL-FPGA-Verilog] 数字锁相环

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
Platform: | Size: 124928 | Author: 于洪彪 | Hits:

[VHDL-FPGA-Verilog] 数字锁相环设计源程序

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF
Platform: | Size: 120832 | Author: 杰轩 | Hits:

[VHDL-FPGA-Verilog] [eda]vhdl

Description: 福州大学EDA选修课所有实验课程代码。VHDL语言描述（vhd），以及电路图（gdf）-Fuzhou University EDA optional courses in all experimental code. VHDL description (vhd), and circuit (GdF)
Platform: | Size: 222208 | Author: 林锋杰 | Hits:

[VHDL-FPGA-Verilog] serial_ppga

Description: 异步串口通信口在FPGA实现，功能有（1）串行数据接收的同步控制；（2）串行数据发送的同步控制-asynchronous serial communication port of the FPGA, function (1) serial data receiver synchronization control; (2) the transmission of serial data synchronization control
Platform: | Size: 199680 | Author: 孙洪亮 | Hits:

[Other] VHDL-FPGA-clock

Description: ＦＰＧＡ数字钟的设计，用VHDL语言编程，max+plus仿真，可在实际电路中验证-FPGA design, VHDL programming, max plus simulation, in the actual circuit verification
Platform: | Size: 269312 | Author: 王越 | Hits:

[transportation applications] gdf

Description: 　根据城市交通路网建设的实际, 研究了描述城市交通网络图的城市道路数据库的组织结构, 在此数据结构的基础上依靠G IS 技术的支持, 采集了大量具体道路信息, 采用D ijk st ra 算法实现了快速最短路径搜索。根据城市的交通状况对交通网络图的边值赋予不同的权值可实现最优路径搜寻, 给出了一个搜索实例——一个包含61 个交通路口的最短路径搜索结果的搜索时间约为1. 1-Urban traffic network in accordance with the actual building, research describing the urban traffic of the urban road network structure of the database, in this data structure based on G IS techniques rely on the support, collecting a large number of specific road information, the use of D ijk st ra algorithm to achieve a fast shortest path search. According to city traffic conditions on the transport network map boundary value given different weights to achieve optimal path search, a search examples are given- one that contains 61 traffic junctions of the shortest path search results of the search time is about 1. 1
Platform: | Size: 183296 | Author: 王功臣 | Hits:

[GDI-Bitmap] GDFViewer

Description: 识别GDF地图文件，画图程序，能够实现对地图文件的基本操作,如移动、放大、缩小、鼠标点击拖动、鼠标点击缩放、动态选择地图层（layer）绘图等。-Identification of GDF map document, drawing procedures, to achieve the basic document on the map operation, such as mobile, enlarge, shrink, drag the mouse to click, mouse click zoom, dynamic selective layer (layer) Drawing.
Platform: | Size: 50176 | Author: ankeer | Hits:

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[Other resource] 数字锁相环设计源程序

[Other resource] [eda]vhdl

[Other] v0.8b

[Other] vhdl

[Other resource] BASED_FLEX10k20_cymometer

[Other resource] gdf

[Other resource] simulation_aufgabe1

[GDI-Bitmap] GDFViewer

[Other resource] 数字锁相环

[VHDL-FPGA-Verilog] 数字锁相环

[VHDL-FPGA-Verilog] 数字锁相环设计源程序

[VHDL-FPGA-Verilog] [eda]vhdl

[VHDL-FPGA-Verilog] serial_ppga

[Other] VHDL-FPGA-clock

[transportation applications] gdf

[GDI-Bitmap] GDFViewer

[VHDL-FPGA-Verilog] Proyekton

[Other] GDF文件解包工具【完整版】

[Other] Altera_QuartusII_13.0_Windows_Crack

[Other] GDF打包解包工具v1.0

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