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[Other resource] 用Verilog HDL实现I2C总线功能 DL : 1: 用Verilog HDL实现I2C总线功能，对I2C总线有很大帮助-with Verilog HDL I2C bus function of I2C bus is very helpful
Update : 2008-10-13 Size : 118.76kb Publisher : 胡路听
[VHDL-FPGA-Verilog] 用Verilog HDL实现I2C总线功能 DL : 1: 用Verilog HDL实现I2C总线功能，对I2C总线有很大帮助-with Verilog HDL I2C bus function of I2C bus is very helpful
Update : 2025-02-17 Size : 118kb Publisher : 胡路听
[VHDL-FPGA-Verilog] I2C总线控制器 Xilinx提供 DL : 0: 用Verilog HDL实现I2C总线功能，对I2C总线有很大帮助-I2C bus contrll functions implemented by Verilog HDL.
Update : 2025-02-17 Size : 869kb Publisher : 司法
[Compress-Decompress algrithms] i2c(FPGA) DL : 1: 基于FPGA的I2C总线模拟，采用verilog HDL语言编写。-FPGA-based I2C bus simulation, using verilog HDL language.
Update : 2025-02-17 Size : 208kb Publisher : 李浩
[Other] I2CbusVHDLVerilogHDL DL : 0: i2c总线verilog源代码，包括测试模块-i2c Bus verilog source code, including testing module
Update : 2025-02-17 Size : 498kb Publisher : 张云凤
[VHDL-FPGA-Verilog] 1_061026140305 DL : 0: 基于FPGA的I2C总线模拟，采用verilog HDL语言编写。- Based on the FPGA I2C main line simulation, uses verilog the HDL language compilation.-FPGA-based I2C bus simulation, using verilog HDL language.- Based on the FPGA I2C main line simulation, verilog uses the HDL language compilation.
Update : 2025-02-17 Size : 200kb Publisher :
[Embeded-SCM Develop] an494_design_example DL : 0: I2C to GPIO Port expander的Verilog HDL 程序原码，直接可在Quartus环境下运行。-I2C to GPIO Port expander procedures of the Verilog HDL source code directly in the Quartus environment.
Update : 2025-02-17 Size : 273kb Publisher : wangyunshann
[VHDL-FPGA-Verilog] I2C(VHDLVerilogHDL) DL : 0: 有两个，一个用VHDL编写的I2C，一个Verilog hdl语言编写的-Have two, one with VHDL prepared I2C, a Verilog hdl languages
Update : 2025-02-17 Size : 502kb Publisher : sunstar
[VHDL-FPGA-Verilog] I2C_Controller DL : 0: I2C控制器的源代码，Verilog HDL语言编写，可以直接调用-I2C controller source code, Verilog HDL language, you can directly call
Update : 2025-02-17 Size : 2kb Publisher : zw
[VHDL-FPGA-Verilog] I2C DL : 0: 用verilog HDL实现I2C Master Controller 的设计，包括主程序设计和测试程序设计-Verilog HDL using I2C Master Controller to achieve the design, including the main program design and test program design
Update : 2025-02-17 Size : 207kb Publisher : zbs
[VHDL-FPGA-Verilog] VerilogHDL_code DL : 0: 几个常用的接口实验的程序代码，用Verilog HDL语言编写的，包括七段数码管、拨码开关、蜂鸣器、矩阵键盘、串口、I2C、跑马灯等。-Some commonly used experimental procedures for the interface code, using Verilog HDL language, including Seven-Segment LED, DIP switch, buzzer, matrix keyboard, serial, I2C, marquees, etc..
Update : 2025-02-17 Size : 1.53mb Publisher : shsh
[Other Embeded program] I2C19861208888 DL : 0: i2c总线模拟，verilog hdl编写的总线模拟控制程序-i2c bus simulation, verilog hdl prepared bus analog control procedures
Update : 2025-02-17 Size : 11kb Publisher : 韩永高
[Other] i2c.tar DL : 0: I2C verilog HDL code including test environment
Update : 2025-02-17 Size : 686kb Publisher : richman
[VHDL-FPGA-Verilog] I2CVerilog DL : 0: I2C 控制器的 Verilog源程序, 适用于FPGA等应用领域-I2C controller Verilog source code,I2C controller Verilog source code
Update : 2025-02-17 Size : 10kb Publisher : babylu
[Embeded-SCM Develop] i2_cmaster DL : 0: verilog HDL i2c主机代码-verilog HDL i2c host code
Update : 2025-02-17 Size : 1kb Publisher : 李爱国
[VHDL-FPGA-Verilog] I2C DL : 0: I2C主机端模块具有avalon-MT总线接口可挂载在Altera soc系统之上使NiosII处理器具备I2C通信能力模块由Verilog HDL编写并经Cyclone II FPGA测试-I2C master modul which has a avalon-MT interface that can be attached to Altera SOC system. It provides NiosII I2C communication capability . This module is written with Verilog HDL and has been tested on a Cyclone II FPGA
Update : 2025-02-17 Size : 6kb Publisher : magic_andy
[File Format] i2c_verilog DL : 0: verilog i2c 控制源代码，包括读写控制-verilog i2c source code control
Update : 2025-02-17 Size : 3kb Publisher : 付工
[VHDL-FPGA-Verilog] i2c DL : 0: verilog hdl file i2c interfacing-verilog hdl file i2c interfacing
Update : 2025-02-17 Size : 2kb Publisher : ved prakash
[Software Engineering] i2c.tar DL : 0: i2c core for verilog hdl
Update : 2025-02-17 Size : 632kb Publisher : mona
[VHDL-FPGA-Verilog] I2C DL : 0: 文档是用Verilog hdl写的I2C源代码，是很不错的一个技术文档。-The document is written in Verilog hdl I2C source code, is a very good technical documentation.
Update : 2025-02-17 Size : 1.44mb Publisher : 欧阳柏林

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