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Description: i2c总线是单片机内部的一种通讯总线，有SCK和SDA两根线组成，根据时序编程输入输出数据，本程序为i2c总线的驱动，留有外接函数接口，可以直接调用
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Size: 1851 |
Author: fly |
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Description: The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control
and data transfer communication between ICs.
Some of the features of the I2C bus are:
• Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A
12V supply line (500mA max.) for powering the peripherals often may be present.
• Each device connected to the bus is software addressable by a unique address and simple
master/ slave relationships exist at all times masters can operate as master-transmitters or as
master-receivers.
• The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data
corruption if two or more masters simultaneously initiate data transfer systems.
• Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 KBit/s in the standard
mode or up to 400 KBit/s in the fast mode.
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Size: 788781 |
Author: lu |
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Description: 提供I2C总线初始化、工作时的启始位、结束位、提供I2C总线的时钟信号，并返回在时钟电平为高期间 SDA信号线上状态。本函数可用于数据发送，也可用于数据接收-provide I2C bus initialization, the Start-end, provide the I2C bus clock signal, the clock and return to the high-level signal line during the SDA state. This function can be used to transmit data, can also be used for data reception
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Size: 1024 |
Author: 陈虹 |
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Description: 本模拟I2C软件包包含了I2C操作的底层子程序，使用前要定义
好SCL和SDA。在标准8051模式(12 Clock)下,对主频要求是不高于12MHz(即1个
机器周期1us) 若Fosc>12MHz则要增加相应的NOP指令数。(总线时序符合I2C标
准模式,100Kbit/S)-simulation package contains the I2C operation of the bottom subroutine, prior to the use of a good definition of SCL and SDA. The standard model 8051 (12 Clock), the speed requirement is no more than 12MHz (that is, a machine cycle TI) if Fosc
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Size: 3072 |
Author: ll |
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Description: #include "intrins.h"
unsigned char SystemError
sbit SCL= P1^6 //定义串行时钟线所在口 使用时根据自己的需要
sbit SDA= P1^7 //定义串行数据线所在口 使用时根据自己的需要
#define SomeNOP() {_nop_() _nop_() _nop_() _nop_() }-# include "intrins.h" unsigned char Syste mError sbit SCL = P1 ^ 6// definition serial clock line where I use according to their needs sbit SDA P1 = ^ 7// definition of serial data lines where I use according to their needs# defin e SomeNOP () (_nop_ () _nop_ () _nop_ () _nop_ (
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Size: 229376 |
Author: zhusheng |
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Description: 这是mcs51下的i2c实现，采用gpio来作为i2c的sda&scl.该实现几乎包含了i2c所有的可能情况！-mcs51 This is the realization of i2c, gpio used as the sda i2c
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Size: 1024 |
Author: timeshift |
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Description: 程序名： 24系列EEPROM读写
电路介绍：由p1.7=sda,p1.6=scl
功能操作：按S3加数，按S1将i2c指定地址数据读出、显示，按S2将指定数据写入-procedures Name : 24 serial EEPROM circuit on literacy : p1.7 = sda, p1.6 = scl functional operation : according to S3 addition, in accordance with S1 i2c designated address will be read out data, display, S2 will be designated by the write data
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Size: 2048 |
Author: 李雨峰 |
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Description: 非常好的一个I2C软件包。本模拟I2C软件包包含了I2C操作的底层子程序，使用前要定义
好SCL和SDA。在标准8051模式(12 Clock)下,对主频要求是不高于12MHz(即1个
机器周期1us) 若Fosc>12MHz则要增加相应的NOP指令数。(总线时序符合I2C标
准模式,100Kbit/S)-A very good package I2C. The simulation package includes I2C operation of the bottom of I2C subroutines, use the former to the definition of good SCL and SDA. 8051 in standard mode (12 Clock) under the requirements of the frequency is not higher than 12MHz (that is, a machine cycle 1us) if the Fosc
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Size: 2048 |
Author: dfdf |
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Description: iic 总线 verilog 源代码
标准i2c总线， 有sda scl 时钟，频率自定-IIC bus standard Verilog source code i2c bus, has sda scl clock, the frequency of self-
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Size: 2048 |
Author: johnnyz |
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Description: 通过并口控制I2C总线的动态库源码，支持自动检测SCL,SDA。-I2C bus through the parallel port to control the dynamic library source to support the automatic detection of SCL, SDA.
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Size: 2543616 |
Author: ssda |
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Description: 在微机上模拟I2C总线的设计中，用并行口的D0（PIN2）模拟SCL信号，用D1（PIN3）模拟SDA信号。根据IIC总线的电平规范-Computer simulation in the design of I2C bus with parallel port D0 (PIN2) simulation SCL signal, with D1 (PIN3) analog signal SDA. According to IIC bus-level norms
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Size: 8192 |
Author: zhuzhijing |
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Description: i2c总线是单片机内部的一种通讯总线，有SCK和SDA两根线组成，根据时序编程输入输出数据，本程序为i2c总线的驱动，留有外接函数接口，可以直接调用-i2c bus is a single-chip internal communications bus, SCK and SDA has two lines, according to timing of data input and output programming, the procedure for the i2c bus driver, left external function interface, can be directly call
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Size: 2048 |
Author: |
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Description: 本源码维MSP430F149控制IIC协议的AD芯片DAC5571，并再1602液晶上显示数据
MCU的P1.0、P1.1 端口与DAC5571 的SDA、SCK端口连接，通过在两个GPIO上模拟
I2C时序从而实现对DAC的操作。可以看到，DAC5571
的输出端Vout连接到了跳线座P7 的第 1 脚。如果用短路帽将跳线座J1 的 2 脚
和 3 脚连接，则DAC的输出直接驱动LED，可以通过LED亮度的变化直观地观察到
DAC输出电压值的变化；如果用短路帽将跳线座J1 的2 脚和1 脚连接，则可以用
MSP430 内置的ADC对DAC输出的电压进行采样转换，对ADC和DAC电路同时进行应用。-MSP430F149-dimensional control of the source of the AD Agreement IIC chip DAC5571, and another 1602 on the display data LCD MCU of P1.0, P1.1 ports of the DAC5571 and SDA, SCK-port connectivity, through two GPIO on I2C timing simulation in order to achieve DAC operation. Can be seen, DAC5571 output Vout is connected to a jumper P7 Block 1 foot. If the cap will short-circuit jumper J1 Block, 2 pin and 3 pin connection, the DAC output to directly drive LED, through the LED brightness can be visually observed changes in DAC output voltage changes in value If the cap will short-circuit jumper Block J1 2 feet and 1 foot to connect, you can use the built-in ADC of the MSP430 output voltage DAC sampling conversion of ADC and DAC circuit applications at the same time.
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Size: 35840 |
Author: skywalker |
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Description: 本程序使用MSP430F149控制IIC总线EEProm AT24C02；MCU的通用输入输出(GPIO)端口P1.2、P1.3 与AT24C02 的SCL、SDA端口相连接构成I2C总线，因为MSP430F149 内部没有专用的I2C接口电路，所以只能用IO端口来模拟I2C时序从而实现对EEPROM的读写操作。从图 3.3 中我们可以看到EEPROM地址选择端口A0~A2 都外接低电平，所以进行I2C通信时，EEPROM的从机地址是唯一的，即A0~A2 所对应的地址控制位均为 0。
因为AT24C0X(X=1,2,4,8,16)系列芯片的管脚是兼容的，所以用户也可以自行更换其他型号的芯片，无需改动任何硬件结构，只需注意器件地址和存储空间寻址模式的变化，相应地修改软件程序即可。
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Size: 40960 |
Author: skywalker |
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Description: 用单片机的I/O口模拟I2C协议
I2C用IO模拟程序网上范例最多的就是51的程序了,这些范例的正确性无需怀疑.但是如果直接以它为蓝本将它"AVR化",一不留神,就会有点问题了.
这要从I2C的硬件规范和AVR及51单片机的IO口说起.I2C要求SCL,SDA二线都有 线与 功能,即I2C驱动口应该是 漏极开路 电路,其高电平的维持是靠上拉电阻来实现的, 而低电平则需要驱动口的强下拉能力.
51单片机IO口正好完全符合这个特性.写起I2C驱动颇为得心应手.但是AVR的IO口强大了,它输出的高电平是实实在在的高电平,而不是靠什么上拉电阻来提供,只有10mA都不到的电流!于是如果直接使用 PORTB_Bit0 = 1这样的操作,就不能满足I2C的线与功能了,如果此时有别的设备要将SCL或者SDA拉低,那么结果就是二个IO口打架,谁赢谁输不得而知,时间长了,多半是两败俱伤,芯片发热吧.
当然AVR的IO口自然有办法满足I2C的电气特性要求,不就是不能输出1么,那么用它的高阻状态即可(DDRB_Bit0=0,PORTB_Bit0=0即可),要输出0么(DDRB_Bit0=1,PORTB_Bit0=0).
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Size: 1576960 |
Author: sanke |
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Description: The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control
and data transfer communication between ICs.
Some of the features of the I2C bus are:
• Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A
12V supply line (500mA max.) for powering the peripherals often may be present.
• Each device connected to the bus is software addressable by a unique address and simple
master/ slave relationships exist at all times masters can operate as master-transmitters or as
master-receivers.
• The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data
corruption if two or more masters simultaneously initiate data transfer systems.
• Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 KBit/s in the standard
mode or up to 400 KBit/s in the fast mode.
Platform: |
Size: 788480 |
Author: lu |
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Description: I2C driver for PIC, PICC compiler - bitbanged. Needs pull-up resistor on SCK and SDA and ports set for open collector -I2C driver for PIC, PICC compiler- bitbanged. Needs pull-up resistor on SCK and SDA and ports set for open collector
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Size: 1024 |
Author: anakron |
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Description: I2C显示程序，主要是通过SDA和SCL两个参数进行设置，数据的发送与接收。-I2C display program, mainly through the SDA and SCL set two parameters, the sending and receiving data.
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Size: 142336 |
Author: 小飞 |
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Description: 语言：verilog
功能：用Verilog HDL编写的I2C主机串行通信的程序。两条总线线路：一条串行数据线 SDA， 一条串行时钟线 SCL；串行的 8 位双向数据传输位速率在标准模式下可达 100kbit/s，快速模式下可达 400kbit/s ，高速模式下可达 3.4Mbit/s；在数据传输过程中，当时钟线为高电平时，数据线必须保持稳定。如果时钟线为高电平时数据线电平发生变化，会被认为是控制信号。
仿真工具：modelsim
综合工具：quartus -Language: verilog
Function: I2C written in Verilog HDL with the host serial communication program. Two bus lines: a serial data line SDA, a serial clock line SCL 8-bit bi-directional serial data transmission bit rate in the standard mode of up to 100kbit/s, fast mode, up to 400kbit/s, high-speed mode of up to 3.4Mbit/s in the data transmission process, when the clock line is high, the data line must remain stable. If the clock line is high level when the data line changes will be considered is the control signal.
Simulation tools: modelsim
synthesis tool: quartus II
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Size: 8192 |
Author: huangjiaju |
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Description: MG82f5d16 I2C SDA SCL Sample code for I2c Protocol
Platform: |
Size: 115535 |
Author: raulpmr33@gmail.com |
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