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[Other resource] 用Verilog HDL实现I2C总线功能

Description: 用Verilog HDL实现I2C总线功能，对I2C总线有很大帮助-with Verilog HDL I2C bus function of I2C bus is very helpful
Platform: | Size: 121607 | Author: 胡路听 | Hits:

[VHDL-FPGA-Verilog] 用Verilog HDL实现I2C总线功能

Description: 用Verilog HDL实现I2C总线功能，对I2C总线有很大帮助-with Verilog HDL I2C bus function of I2C bus is very helpful
Platform: | Size: 120832 | Author: 胡路听 | Hits:

[VHDL-FPGA-Verilog] I2C总线控制器 Xilinx提供

Description: 用Verilog HDL实现I2C总线功能，对I2C总线有很大帮助-I2C bus contrll functions implemented by Verilog HDL.
Platform: | Size: 889856 | Author: 司法 | Hits:

[VHDL-FPGA-Verilog] I2CSlave

Description: Verilog HDL实现的I2C Slave模拟-achieve the Verilog HDL simulation I2C Slave
Platform: | Size: 1024 | Author: lzy | Hits:

[Compress-Decompress algrithms] i2c(FPGA)

Description: 基于FPGA的I2C总线模拟，采用verilog HDL语言编写。-FPGA-based I2C bus simulation, using verilog HDL language.
Platform: | Size: 212992 | Author: 李浩 | Hits:

[Other] I2CbusVHDLVerilogHDL

Description: i2c总线verilog源代码 ，包括测试模块-i2c Bus verilog source code, including testing module
Platform: | Size: 509952 | Author: 张云凤 | Hits:

[VHDL-FPGA-Verilog] 1_061026140305

Description: 基于FPGA的I2C总线模拟，采用verilog HDL语言编写。- Based on the FPGA I2C main line simulation, uses verilog the HDL language compilation.-FPGA-based I2C bus simulation, using verilog HDL language.- Based on the FPGA I2C main line simulation, verilog uses the HDL language compilation.
Platform: | Size: 204800 | Author: | Hits:

[Com Port] uart2iic

Description: UART转I2C的Verilog HDL代码，由北京邮电大学《VerilogHDL设计与EDA技术基础》教师编写-UART to I2C of the Verilog HDL code, by the Beijing University of Posts and Telecommunications VerilogHDL design and EDA technology infrastructure Teacher preparation
Platform: | Size: 3072 | Author: emulous | Hits:

[Com Port] demo_24c01a

Description: 24C01A的Verilog HDL仿真代码，用于I2C接口模块的测试，由北京邮电大学《VerilogHDL设计与EDA技术基础》教师编写-24C01A simulation of Verilog HDL code for the I2C interface module of the test, by the Beijing University of Posts and Telecommunications VerilogHDL design and EDA technology infrastructure Teacher preparation
Platform: | Size: 1024 | Author: emulous | Hits:

[Embeded-SCM Develop] an494_design_example

Description: I2C to GPIO Port expander的Verilog HDL 程序原码，直接可在Quartus环境下运行。-I2C to GPIO Port expander procedures of the Verilog HDL source code directly in the Quartus environment.
Platform: | Size: 279552 | Author: wangyunshann | Hits:

[VHDL-FPGA-Verilog] I2C_SP

Description: 华为Verilog HDL 入门教程，下载后请解压。-Huawei Tutorial Verilog HDL, after downloading, please unzip.
Platform: | Size: 265216 | Author: shaoyqo | Hits:

[VHDL-FPGA-Verilog] I2C(VHDLVerilogHDL)

Description: 有两个，一个用VHDL编写的I2C，一个Verilog hdl语言编写的-Have two, one with VHDL prepared I2C, a Verilog hdl languages
Platform: | Size: 514048 | Author: sunstar | Hits:

[VHDL-FPGA-Verilog] I2C_Controller

Description: I2C控制器的源代码，Verilog HDL语言编写，可以直接调用-I2C controller source code, Verilog HDL language, you can directly call
Platform: | Size: 2048 | Author: zw | Hits:

[VHDL-FPGA-Verilog] I2C

Description: 用verilog HDL实现I2C Master Controller 的设计，包括主程序设计和测试程序设计-Verilog HDL using I2C Master Controller to achieve the design, including the main program design and test program design
Platform: | Size: 211968 | Author: zbs | Hits:

[Other Embeded program] I2C19861208888

Description: i2c总线模拟，verilog hdl编写的总线模拟控制程序-i2c bus simulation, verilog hdl prepared bus analog control procedures
Platform: | Size: 11264 | Author: 韩永高 | Hits:

[Other] i2c.tar

Description: I2C verilog HDL code including test environment
Platform: | Size: 702464 | Author: richman | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 通过I2C接口读写EEPROM 在本项目中，我们利用Verilog HDL实现了部分I2C总线功能，并能够通过该总线对AT24C02进行读写操作。为了便于观察读写eeprom的结果，我们将读写的数据同时显示在七段数码管上，并设定读写的数据从0到255不断循环，这样就可以方便进行比较。 -Through the I2C interface to read and write EEPROM in this project, we use Verilog HDL to achieve some of the I2C bus function, and can be carried out through the bus, read and write operations on the AT24C02. To read and write eeprom in order to facilitate observation of the results, we will read and write data simultaneously displayed in the seven-segment digital tube, and set read and write data from 0 to 255 in cycles, so that can be easily compared.
Platform: | Size: 8192 | Author: andy | Hits:

[Software Engineering] i2c.tar

Description: i2c core for verilog hdl
Platform: | Size: 647168 | Author: mona | Hits:

[VHDL-FPGA-Verilog] i2c

Description: 标准I2c读写时序，verilog Hdl-Standard I2c read and write timing, verilog Hdl
Platform: | Size: 3072 | Author: wangminghui | Hits:

[VHDL-FPGA-Verilog] I2C

Description: 语言：verilog 功能：用Verilog HDL编写的I2C主机串行通信的程序。两条总线线路：一条串行数据线 SDA， 一条串行时钟线 SCL；串行的 8 位双向数据传输位速率在标准模式下可达 100kbit/s，快速模式下可达 400kbit/s ，高速模式下可达 3.4Mbit/s；在数据传输过程中，当时钟线为高电平时，数据线必须保持稳定。如果时钟线为高电平时数据线电平发生变化，会被认为是控制信号。 仿真工具：modelsim 综合工具：quartus -Language: verilog Function: I2C written in Verilog HDL with the host serial communication program. Two bus lines: a serial data line SDA, a serial clock line SCL 8-bit bi-directional serial data transmission bit rate in the standard mode of up to 100kbit/s, fast mode, up to 400kbit/s, high-speed mode of up to 3.4Mbit/s in the data transmission process, when the clock line is high, the data line must remain stable. If the clock line is high level when the data line changes will be considered is the control signal. Simulation tools: modelsim synthesis tool: quartus II
Platform: | Size: 8192 | Author: huangjiaju | Hits:
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