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[Software Engineering] VHDL

Description: 本系统使用VHDL语言进行设计，采用自上向下的设计方法。目标器件选用Xilinx公司的FPGA器件，并利用Xilinx ISE 7.1 进行VHDL程序的编译与综合，然后用Modelsim Xilinx Edition 6.1进行功能仿真和时序仿真。
Platform: | Size: 297917 | Author: 西西 | Hits:

[Other resource] 8086FPGA

Description: xilinx ise 7.1下实现sparten3 basys板上基于8086FPGA软核的吃豆子游戏
Platform: | Size: 2360627 | Author: 朱万里 | Hits:

Description: 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 这个实例实现通过ModelSim工具实现一个具有“百分秒，秒，分”计时功能的数字跑表； 2. 工程在project文件夹中，双击paobiao.ise文件打开工程； 3. 源文件在rtl文件夹中，paobiao.v为设计文件，paobiao_tb.tbw是仿真测试文件； 4. 打开工程后，在工程浏览器中选择paobiao_tb.tbw，在Process View中双击“Simulation Behavioral Model”选项，若正确安装ModelSim，系统将自动打开ModelSim进行行为仿真，运行仿真即可得到仿真结果。
Platform: | Size: 156342 | Author: 李华 | Hits:

[Other resource] traffic_control

Description: 软件开发环境：ISE 7.1i 仿真环境：ISE Simulator 1. 这个实例实现通过ISE Simulator工具实现一个具有两个方向共八个灯的交通灯控制器； 2. 工程在project文件夹中，双击traffic.ise文件打开工程； 3. 源文件在rtl文件夹中，traffic.v为设计文件，traffic_tb.tbw是仿真波形文件； 4. 打开工程后，在工程浏览器中选择traffic_tb.tbw，在Process View中双击“Simulation Behavioral Model”选项，进行行为仿真，即可得到仿真结果。
Platform: | Size: 249362 | Author: 李华 | Hits:

[Other resource] ISE7-1_Step_by_step

Description: ISE 7.1使用教程，对于初学者进行step-by-step的ISE7.1使用说明
Platform: | Size: 1229243 | Author: xiaoyan | Hits:

[VHDL-FPGA-Verilog] hourse_race_light(7seg)

Description: 这是我用Xilnx公司的sparten3 FPGA开发板上，用集成开发环境ISE设计制作的一个跑马灯程序，就如同一个小型的霓虹灯。供大家参考。-This is the company I used Xilnx the sparten3 FPGA development board. use integrated development environment ISE design of a Bomadeng procedures, it is like a small neon lights. For your reference.
Platform: | Size: 7168 | Author: 汪莉莉 | Hits:

[Software Engineering] VHDL

Description: 本系统使用VHDL语言进行设计，采用自上向下的设计方法。目标器件选用Xilinx公司的FPGA器件，并利用Xilinx ISE 7.1 进行VHDL程序的编译与综合，然后用Modelsim Xilinx Edition 6.1进行功能仿真和时序仿真。-The system design using VHDL language, using top-down design method. Selection of the target device Xilinx
Platform: | Size: 297984 | Author: 西西 | Hits:

[VHDL-FPGA-Verilog] 8086FPGA

Description: xilinx ise 7.1下实现sparten3 basys板上基于8086FPGA软核的吃豆子游戏-xilinx ise 7.1 under sparten3 basys board based on soft-core 8086FPGA eating beans games
Platform: | Size: 2360320 | Author: 朱万里 | Hits:

[VHDL-FPGA-Verilog] Des2Sim

Description: 本文介绍了一个使用 VHDL 描述计数器的设计、综合、仿真的全过程，作为我这一段时间自学 FPGA/CPLD 的总结，如果有什么不正确的地方，敬请各位不幸看到这篇文章的大侠们指正，在此表示感谢。当然，这是一个非常简单的时序逻辑电路实例，主要是详细描述了一些软件的使用方法。文章中涉及的软件有Synplicity 公司出品的Synplify Pro 7.7.1； Altera 公司出品的 Quartus II 4.2；Mentor Graphics 公司出品的 ModelSim SE 6.0。 -This article describes a VHDL description of the use of counter design, synthesis, simulation of the entire process, this time as my self-FPGA/CPLD summary, if what has not the right place, please see this article that, unfortunately, the heroes They correct me, wish to express my gratitude. Of course, this is a very simple example of sequential logic circuit is mainly a detailed description of a number of software usage. Article involved in the software company has produced Synplicity
Platform: | Size: 1945600 | Author: 黄鹏曾 | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 这个实例实现通过ModelSim工具实现一个具有“百分秒，秒，分”计时功能的数字跑表； 2. 工程在project文件夹中，双击paobiao.ise文件打开工程； 3. 源文件在rtl文件夹中，paobiao.v为设计文件，paobiao_tb.tbw是仿真测试文件； 4. 打开工程后，在工程浏览器中选择paobiao_tb.tbw，在Process View中双击“Simulation Behavioral Model”选项，若正确安装ModelSim，系统将自动打开ModelSim进行行为仿真，运行仿真即可得到仿真结果。-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.01. Realize this instance through the ModelSim tool realize a
Platform: | Size: 155648 | Author: 李华 | Hits:

[VHDL-FPGA-Verilog] traffic_control

Description: 软件开发环境：ISE 7.1i 仿真环境：ISE Simulator 1. 这个实例实现通过ISE Simulator工具实现一个具有两个方向共八个灯的交通灯控制器； 2. 工程在project文件夹中，双击traffic.ise文件打开工程； 3. 源文件在rtl文件夹中，traffic.v为设计文件，traffic_tb.tbw是仿真波形文件； 4. 打开工程后，在工程浏览器中选择traffic_tb.tbw，在Process View中双击“Simulation Behavioral Model”选项，进行行为仿真，即可得到仿真结果。-Software development environment: ISE 7.1i simulation environment: ISE Simulator1. Realize this instance through the ISE Simulator tool to achieve a total of eight lights in both directions of traffic lights controller 2. Works project folder, double-click traffic.ise Open the project document 3. rtl source file in the folder, traffic.v for design documents, traffic_tb.tbw is the simulation waveform files 4. to open a project, the project browser, select traffic_tb.tbw, in the Process View in the double hit
Platform: | Size: 248832 | Author: 李华 | Hits:

[Other] ISE7-1_Step_by_step

Description: ISE 7.1使用教程，对于初学者进行step-by-step的ISE7.1使用说明-Using ISE 7.1 Tutorial for beginners to step-by-step instructions of ISE7.1
Platform: | Size: 1228800 | Author: xiaoyan | Hits:

[VHDL-FPGA-Verilog] song

Description: 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 梁祝乐曲演奏电路-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Butterfly music concert circuit
Platform: | Size: 1024 | Author: 许毅民 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 多功能数字钟-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Multi-function digital clock
Platform: | Size: 1024 | Author: 许毅民 | Hits:

[VHDL-FPGA-Verilog] sell

Description: 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 自动售饮机电话计费器程序-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Drink vending machine telephone billing program
Platform: | Size: 1024 | Author: 许毅民 | Hits:

[VHDL-FPGA-Verilog] naozhongsheji

Description: 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 闹钟设计-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Alarm Clock Design
Platform: | Size: 288768 | Author: 许毅民 | Hits:

[VHDL-FPGA-Verilog] yuelao

Description: 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 用VHDL语言仿真歌曲刘德华的《月老》-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Using VHDL simulation language song Andy Lau' s " 月老"
Platform: | Size: 214016 | Author: 许毅民 | Hits:

[Other] mcu_8

Description: 使用函数实现简单的八位处理器软件开发环境：ISE 7.1i 仿真环境：ISE Simulator 1. 这个实例实现通过ISE Simulator工具实现一个可以进行两个八位操作数四种操作的简单处理器； 2. 工程在project文件夹中，双击mpc.ise文件打开工程； 3. 源文件在rtl文件夹中，mpc.v为设计文件，mpc_tb.tbw是仿真波形文件； 4. 打开工程后，在工程浏览器中选择mpc_tb.tbw，在Process View中双击“Simulation Behavioral Model”选项，进行行为仿真，即可得到仿真结果。-The use of a simple function to achieve the eight-processor software development environment: ISE 7.1i simulation environment: ISE Simulator 1. This example through the ISE Simulator tool to achieve the realization of a two operand four of eight simple processor operation 2. works in the project folder, double-click to open the project file mpc.ise 3. rtl source file in the folder, mpc.v documents for the design, mpc_tb.tbw is the simulation waveform files 4. to open a project, a browser in the works Select device mpc_tb.tbw, double-click in the Process View in the " Simulation Behavioral Model" option, to carry out acts of simulation, simulation results can be obtained.
Platform: | Size: 221184 | Author: 王磊 | Hits:

[VHDL-FPGA-Verilog] 45561564

Description: 典型实例10.8 字符LCD接口的设计与实现软件开发环境：ISE 7.1i 硬件开发环境：红色飓风II代－Xilinx版 1. 本实例控制开发板上面的LCD的显示； 2. 工程在\project文件夹里面 3. 源文件和管脚分配在\rtl文件夹里面 4. 下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Typical examples of character LCD interface 10.8 The Design and Implementation of Software Development Environment: ISE 7.1i development environment hardware: Hurricane II on behalf of the red-Xilinx Edition 1. The above examples of the control board of the LCD display 2. Projects \ project folder inside 3. the distribution of the source file and pin in \ rtl folder inside 4. download files in \ download folder inside,. mcs file for the PROM mode download,. bit for the JTAG debugger to download the file.
Platform: | Size: 313344 | Author: 王磊 | Hits:

[Other] ISE7.1

Description: ise 中文使用手册，详细介绍如何使用ise，附大量图片说明-ise Chinese user manual details how to use the ise, attached to a large number of captions
Platform: | Size: 277504 | Author: xinghuo | Hits:

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[Software Engineering] VHDL

[Other resource] 8086FPGA

[Other resource] paobiao

[Other resource] traffic_control

[Other resource] ISE7-1_Step_by_step

[VHDL-FPGA-Verilog] hourse_race_light(7seg)

[Software Engineering] VHDL

[VHDL-FPGA-Verilog] 8086FPGA

[VHDL-FPGA-Verilog] Des2Sim

[VHDL-FPGA-Verilog] paobiao

[VHDL-FPGA-Verilog] traffic_control

[Other] ISE7-1_Step_by_step

[VHDL-FPGA-Verilog] song

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] sell

[VHDL-FPGA-Verilog] naozhongsheji

[VHDL-FPGA-Verilog] yuelao

[Other] mcu_8

[VHDL-FPGA-Verilog] 45561564

[Other] ISE7.1

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