Search - MAX II CPLD

[Other resource] an485_design_example

Description: AN485_CH-MAX II CPLD 中的串行外设接口主机（verilog SPI）
Platform: | Size: 312581 | Author: zhiqiang | Hits:

[Software Engineering] an500_design_example

Description: 利用MAX II CPLD 实现 NAND 闪存接口
Platform: | Size: 192030 | Author: spark | Hits:

[Other resource] an500_CN

Description: 利用MAX II CPLD 实现 NAND 闪存接口
Platform: | Size: 205271 | Author: spark | Hits:

[Other resource] FT245BM

Description: 这是一个在MAX II CPLD利用FT245BM 模块实现USB传输的读写程序，用的是Verilog HDL语言
Platform: | Size: 975764 | Author: 杨林成 | Hits:

[Software Engineering] MAXII_application_handbook(chinese)

Description: MAX II CPLD具有灵活的可编程接口，合并了分立的FLASH存储器件，能快速和容易地配置FPGA，DSP，ASIC等。本中文手册将让用户对CPLD有一个宏观的认识。
Platform: | Size: 990408 | Author: pantree | Hits:

[Communication] maxplus2

Description: 关于CPLD的文章不错的! 可以给菜菜参考下-article on the CPLD good! Can either under reference
Platform: | Size: 17325056 | Author: 许辉 | Hits:

[VHDL-FPGA-Verilog] CPLDxiaoche

Description: 智能机器小车主要完成寻迹功能，由机械结构和控制单元两个部分组成。机械结构是一个由底盘、前后辅助轮、控制板支架、传感器支架、左右驱动轮、步进电机等组成。控制单元部分主要由主要包含传感器及其调理电路、步进电机及驱动电路、控制器三个部分。本设计的核心为控制器部分，采用Altera MAX7000S系列的EPM7064LC84-15作主控芯片。CPLD芯片的设计主要在MAX+plusⅡ10.0环境下利用VHDL语言编程实现。驱动步进电机电路主要利用ULN2803作为驱动芯片。 -intelligent machines trolley track of the major functions by mechanical structure and control modules of two components. Mechanical structure is a chassis, after supporting wheels, the control panel stent, sensors stent, driving wheel around, Stepper motors, and other components. Some of the main control unit from the mainly contains sensors and conditioning circuits, and stepper motor drive circuit, the controller of three parts. The design for the core controller, Altera MAX7000S the EPM7064LC84-15 for the control chip. CPLD chip design mainly in MAX II plus 10.0 environment using VHDL programming. Stepper motor driver circuit using mainly driven ULN2803 chip.
Platform: | Size: 1024 | Author: lili | Hits:

[VHDL-FPGA-Verilog] an485_design_example

Description: AN485_CH-MAX II CPLD 中的串行外设接口主机（verilog SPI）
Platform: | Size: 312320 | Author: zhiqiang | Hits:

[Software Engineering] an500_design_example

Description: 利用MAX II CPLD 实现 NAND 闪存接口-MAX II CPLD realize the use of NAND flash memory interface
Platform: | Size: 191488 | Author: spark | Hits:

[SCM] an500_CN

Description: 利用MAX II CPLD 实现 NAND 闪存接口-MAX II CPLD realize the use of NAND flash memory interface
Platform: | Size: 204800 | Author: spark | Hits:

[VHDL-FPGA-Verilog] FT245BM

Description: 这是一个在MAX II CPLD利用FT245BM 模块实现USB传输的读写程序，用的是Verilog HDL语言-This is a MAX II CPLD module using USB transmit FT245BM reading and writing process, using Verilog HDL language
Platform: | Size: 975872 | Author: 杨林成 | Hits:

[Software Engineering] MAXII_application_handbook(chinese)

Description: MAX II CPLD具有灵活的可编程接口，合并了分立的FLASH存储器件，能快速和容易地配置FPGA，DSP，ASIC等。本中文手册将让用户对CPLD有一个宏观的认识。-MAX II CPLD with a flexible programmable interface, the merger of the separation of FLASH memory, can quickly and easily configure the FPGA, DSP, ASIC, etc.. Chinese manual will allow users to have a macro on the CPLD awareness.
Platform: | Size: 990208 | Author: pantree | Hits:

[Software Engineering] an497_CN

Description: 利用MAX II CPLD 实现LCD 控制器-MAX II CPLD realization of the use of LCD Controller
Platform: | Size: 254976 | Author: 广州老赵 | Hits:

[SCM] altera_epm1270_MAX

Description: 一个ALTERA公司EPM1270 cpld的实验板原理图，其中有PCI接口电路，PDF格式-A ALTERA Corporation EPM1270 cpld schematic diagram of the experimental board, including PCI interface circuit, PDF format
Platform: | Size: 240640 | Author: blur | Hits:

[VHDL-FPGA-Verilog] Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_E

Description: Example VHDL project showing how to use a PWM by CPLD
Platform: | Size: 290816 | Author: maros | Hits:

[VHDL-FPGA-Verilog] MAXII_Device_Handbook

Description: Altera 公司生产的CPLD系列中的低端高性能产品MAXII用户手册,这个也能从Altera官方网站上下载。-Altera' s CPLD series production of low-end high-performance products MAXII user' s manual, this is also downloaded from the Altera website.
Platform: | Size: 2846720 | Author: carris | Hits:

[Documents] an428

Description: MAX II CPLD 设计手册英文版-MAX II CPLD Design Guidelines
Platform: | Size: 284672 | Author: shufeng | Hits:

[VHDL-FPGA-Verilog] Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Ex

Description: 来自于ALTERA官方网站。本文档详细介绍怎样利用MAX® II CPLD 来实现脉冲宽度调制(PWM)。本设计还利用了MAX II CPLD 的内部用户闪存振荡器，不需要采用专门的外部时钟。附有verilog源程序。-From ALTERA website. This document details how to use the MAX ® II CPLD to implement pulse width modulation (PWM). This design also uses the MAX II CPLD' s internal oscillator user flash memory, without using a special external clock. With verilog source.
Platform: | Size: 291840 | Author: 无小品 | Hits:

[VHDL-FPGA-Verilog] 9B96_EB_V1.0

Description: ARM Cortex-M3（LM3S9B96） + MAX II CPLD（EPM1270）实验板原理图-ARM Cortex-M3 (LM3S9B96)+ MAX II CPLD (EPM1270) test board schematic
Platform: | Size: 90112 | Author: 绿风 | Hits:

[VHDL-FPGA-Verilog] ourdev_536218

Description: 利用 MAX II CPLD 实现移动 SDRAM 接口-Using MAX II CPLD to implement mobile SDRAM Interface
Platform: | Size: 192512 | Author: LQH | Hits:

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[Other resource] an485_design_example

[Software Engineering] an500_design_example

[Other resource] an500_CN

[Other resource] FT245BM

[Software Engineering] MAXII_application_handbook(chinese)

[Communication] maxplus2

[VHDL-FPGA-Verilog] CPLDxiaoche

[VHDL-FPGA-Verilog] an485_design_example

[Software Engineering] an500_design_example

[SCM] an500_CN

[VHDL-FPGA-Verilog] FT245BM

[Software Engineering] MAXII_application_handbook(chinese)

[Software Engineering] an497_CN

[SCM] altera_epm1270_MAX

[VHDL-FPGA-Verilog] Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_E

[VHDL-FPGA-Verilog] MAXII_Device_Handbook

[Documents] an428

[VHDL-FPGA-Verilog] Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Ex

[VHDL-FPGA-Verilog] 9B96_EB_V1.0

[VHDL-FPGA-Verilog] ourdev_536218

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