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[VHDL-FPGA-Verilog] 用modelsim仿真一个正弦波产生程序

Description: 用modelsim仿真一个正弦波产生程序-modelsim simulation using a sine wave generated procedures
Platform: | Size: 68608 | Author: 阿乐 | Hits:

[VHDL-FPGA-Verilog] Modelsim中文教程

Description: Modelsim中文教程,有３篇讲Modelsim的资料，对新手是个很好的参考资料-Modelsim Chinese guide, a three stresses Modelsim information, the rookie is a very good reference!
Platform: | Size: 970752 | Author: 温暖感 | Hits:

[Other Databases] Xilinx-modelsim-library

Description: Xilinx的modelsim　仿真库！里面有许多库函数，对于ｖｌｏｇ或ｖｈｄｌ编程有很多好的源代码可以剪切！-Xilinx modelsim simulation library! There are many libraries, vlog or VHDL programming a lot of good source code can shear!
Platform: | Size: 32190464 | Author: 杨俊涛 | Hits:

[VHDL-FPGA-Verilog] FFT_CORE

Description: FFT算法的VHDL语言实现 可在Modelsim上运行和调试 -FFT algorithm VHDL in the operation and Modelsim Debugging
Platform: | Size: 29696 | Author: 紫蓝 | Hits:

[VHDL-FPGA-Verilog] ModelSim_TestBench_VHDL

Description: ModelSim TestBench的VHDL模版-ModelSim VHDL template TestBench
Platform: | Size: 1024 | Author: 汤维 | Hits:

[VHDL-FPGA-Verilog] Freq_counter

Description: 本代码介绍了使用VHDL开发FPGA的一般流程，最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL，在软件开发平台ISE上完成，可以在较高速时钟频率（100MHz）下正常工作。该设计的频率计能准确的测量频率在1Hz到100MHz之间的信号。使用ModelSim仿真软件对VHDL程序做了仿真，并完成了综合布局布线，最终下载到芯片Spartan-II上取得良好测试效果。-the code on the FPGA using VHDL development of the general process, finally adopted a FPGA-based digital frequency method. The design using VHDL hardware description language, the software development platform ISE completed, the higher speed clock frequency (100MHz) under normal work. The design of the frequency meter can be accurately measured in a frequency of 100MHz between Hz signal. Use ModelSim VHDL simulation software to do the simulation process, and completed a comprehensive layout cabling, downloaded to the final chip Spartan-II made good on the test results.
Platform: | Size: 515072 | Author: 许的开 | Hits:

[VHDL-FPGA-Verilog] vhdlYONGHUSHOUCE

Description: 非常优秀的国外VHDL设计教程，可进行MODELSIM模拟等操作-Excellent foreign VHDL design tutorial, it can conduct operations such as ModelSim Simulation
Platform: | Size: 2766848 | Author: yyy | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: VHDL控制步进电机原理PDF文档非常有用，看看吧-VHDL control of stepper motor principle of PDF files is very useful to see it
Platform: | Size: 199680 | Author: 王攀 | Hits:

[VHDL-FPGA-Verilog] modelsim

Description: 基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256点的fft -Memory based on the base 4 by the frequency of fft taken the VHDL description of the continuous data stream can be carried out 256 point fft
Platform: | Size: 22528 | Author: 庞志勇 | Hits:

[Software Engineering] VHDL

Description: 本系统使用VHDL语言进行设计，采用自上向下的设计方法。目标器件选用Xilinx公司的FPGA器件，并利用Xilinx ISE 7.1 进行VHDL程序的编译与综合，然后用Modelsim Xilinx Edition 6.1进行功能仿真和时序仿真。-The system design using VHDL language, using top-down design method. Selection of the target device Xilinx
Platform: | Size: 297984 | Author: 西西 | Hits:

[VHDL-FPGA-Verilog] (Modelsim)simulation

Description: 这是关于VHDL编程仿真的东西,大家感兴趣的话可以下载.原文并不是这个名字,里边有三个文件.-This is a simulation on the VHDL programming things, everyone interested can be downloaded. This is not the original name, has three documents inside.
Platform: | Size: 67584 | Author: madder | Hits:

[ARM-PowerPC-ColdFire-MIPS] mips3

Description: modelsim+dc开发的4级流水线结构的MIPS CPU，完成基本的逻辑运算和跳转。测试程序为希尔排序，结果正确。-modelsim+ dc development of four pipelined structure MIPS CPU, the completion of the basic logic operations and Jump. Test procedure for the Hill to sort the results correctly.
Platform: | Size: 307200 | Author: 杨春 | Hits:

[VHDL-FPGA-Verilog] Modelsim

Description: 不错的Quartus II 与modelsim结合仿真简介笔记，较为适合初学者，希望对大家有帮助！
Platform: | Size: 1357824 | Author: 刘英 | Hits:

[Other] ModelSim

Description: ModelSim初学者教程，通过本文档可以快速了解该软件的使用！-ModelSim Tutorial for beginners, through this document can quickly understand the use of the software!
Platform: | Size: 527360 | Author: 王海 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设 计，包括偶数分频、非 50％占空比和 50％占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使 用的电路，并在 ModelSim 上进行验证。 -This article describes the use of examples in the FPGA/CPLD prescaler to use VHDL to design, including the even-numbered sub-frequency, non-50 duty cycle and 50 duty cycle of the odd-numbered sub-frequency, semi-integer (N+ 0.5) sub-frequency, fractional-N, as well as scores of sub-band frequency points. All can realize through the Synplify Pro or FPGA manufacturers integrated synthesizer to form a circuit can be used and verified in the ModelSim on.
Platform: | Size: 322560 | Author: 黄鹏曾 | Hits:

[VHDL-FPGA-Verilog] Des2Sim

Description: 本文介绍了一个使用 VHDL 描述计数器的设计、综合、仿真的全过程，作为我这一段 时间自学 FPGA/CPLD 的总结，如果有什么不正确的地方，敬请各位不幸看到这篇文章的 大侠们指正，在此表示感谢。当然，这是一个非常简单的时序逻辑电路实例，主要是详细 描述了一些软件的使用方法。文章中涉及的软件有Synplicity 公司出品的Synplify Pro 7.7.1； Altera 公司出品的 Quartus II 4.2；Mentor Graphics 公司出品的 ModelSim SE 6.0。 -This article describes a VHDL description of the use of counter design, synthesis, simulation of the entire process, this time as my self-FPGA/CPLD summary, if what has not the right place, please see this article that, unfortunately, the heroes They correct me, wish to express my gratitude. Of course, this is a very simple example of sequential logic circuit is mainly a detailed description of a number of software usage. Article involved in the software company has produced Synplicity
Platform: | Size: 1945600 | Author: 黄鹏曾 | Hits:

[VHDL-FPGA-Verilog] modelsim

Description: modelsim 使用教程,verilog或vhdl仿真-ModelSim use tutorial, verilog or VHDL simulation
Platform: | Size: 487424 | Author: hxl | Hits:

[Software Engineering] ModelSim_example

Description: modelsim仿真流程，附有两个源码（vhdl),做设计例子，按步骤操作并添加源码，即可看到仿真波形输出-ModelSim simulation process, with the two source code (vhdl), to do a design example, according to these steps and add the source, you can see the simulation waveform output
Platform: | Size: 197632 | Author: tianrongcai | Hits:

[source in ebook] XiaYuWen_8_RISC_CPU

Description: 夏宇闻8位RISC_CPU的完整代码+TESTBENCH（已调试） modelsim工程文件，包括书中所测试的三个程序和相关数据，绝对可用~所有信号名均遵从原书。在论坛中没有找到testbench的，只有一个mcu的代码，但很多和书中的是不一样的，自己改了下下~`````大家多多支持啊~`我觉得书中也还是有些不尽如人意的地方，如clk_gen.v中clk2,clk4是没有用的，assign clk1=~clk再用clk1的negedge clk1来触发各个module也是不太好的，会使时序恶化，综合时很可能会setup vio的，所以觉得直接用clk的上升沿来触发各个module比较好-XIA Yu-Wen 8 RISC_CPU complete code+ TESTBENCH (has debug) modelsim project documents, including the book by the three test procedures and related data, the absolute available ~ all signals were found in compliance with the original name. Not found in the forums Testbench, and there is only one mcu code, but many and the book is not the same as he changed a lot of support under the U.S. ~````` ah ~ `I think the book is still some uncertainty unsatisfactory places, such as clk_gen.v in clk2, clk4 is of no use, assign clk1 = ~ clk reuse CLK1 of negedge clk1 to trigger module is not all good, cause the deterioration of timing, synthesis is likely to setup vio, therefore, feel that the direct use of the rising edge of clk to trigger each module is better
Platform: | Size: 86016 | Author: 刘志伟 | Hits:

[Software Engineering] Modelsim

Description: modelsim 使用笔记 初学ModelSimSE时被迷糊了几天的若干概念.pdf 等-Notes ModelSimSE beginner modelsim use was confused for a few days a number of concepts. pdf, etc.
Platform: | Size: 1357824 | Author: 牛川 | Hits:
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