Search - PLL verilog

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[Other Embeded program] verilogpll DL : 0: 用verilog语言编写的全数字锁相环的源代码,基于fpga平台-using Verilog language prepared by the DPLL the source code, they simply based on the platform
Update : 2025-02-17 Size : 3kb Publisher : letheo
[VHDL-FPGA-Verilog] ADPLL DL : 2: verilog ADPLL file with testbench.v
Update : 2025-02-17 Size : 25kb Publisher :
[Wavelet] verilogpll1234 DL : 0: 基于verilog的全数字锁相环的设计，基于verilog的全数字锁相环的设计。-verilog DPLL the design, verilog based on the DPLL design.
Update : 2025-02-17 Size : 91kb Publisher : li
[Software Engineering] xp2syscloclkpll DL : 0: 这个是讲pll的具体用法的,一般在fpga设计中都会用到他,这个是lattice的xp2的pll的介绍,不过,fpga 都是相通的其他两家也差不多-Pll say this is the specific usage, the general design in the FPGA will use him, this is the lattice of the pll of xp2 introduction, however, fpga are connected to other two similar
Update : 2025-02-17 Size : 626kb Publisher :
[Program doc] DDS DL : 0: FPGA中实现基于查找表方式（LUT）的DDS实现，可用在数字下变频和COSTAS锁相环中，Verilog编写，本人已经调通-In FPGA-based lookup table approach (LUT) to achieve the DDS can be used in the digital down-conversion and COSTAS PLL, Verilog prepared, I have transferred Qualcomm
Update : 2025-02-17 Size : 145kb Publisher :
[VHDL-FPGA-Verilog] dpll_demo DL : 0: 一个实现简单的数字锁相环Verilog代码，本人借鉴网上现有的代码后经修改在Cyclone II上调通实现，里面有ModelSim仿真成功的波形图-A simple digital PLL Verilog code, I draw on-line after the existing code, as amended, pass upward in the Cyclone II realized, there are successful ModelSim Simulation Waveform
Update : 2025-02-17 Size : 66kb Publisher :
[DSP program] PLL DL : 0: 可以实现自动锁相环功能的C源程序代码模块，-Can be achieved automatically PLL function C source code modules,
Update : 2025-02-17 Size : 6kb Publisher : 刘磊
[VHDL-FPGA-Verilog] PLL DL : 0: verilog PLL的代码，和PLL 的功能介绍，希望能通过，只是简单了点-verilog PLL code, and the function of PLL, the hope, but simply a point
Update : 2025-02-17 Size : 18kb Publisher : gjj
[Other] pll_funcnl DL : 0: pll in verilog in the Appendix
Update : 2025-02-17 Size : 222kb Publisher : jadedfox
[Industry research] pll_verilog DL : 0: verilog model of a P-verilog model of a PLL
Update : 2025-02-17 Size : 132kb Publisher : jadedfox
[Other] pll_verilog_code DL : 0: 这是一段pll verilog代码，是本人转载！-This is a period of pll verilog code, yes I reprint!
Update : 2025-02-17 Size : 3kb Publisher : 海天之洲
[Communication-Mobile] EP2C8_pll_example DL : 0: EP2C8 PLL例化的例子,给不会的人做个参考.专门写的一个.呵呵.不过是Verilog的.-EP2C8 PLL cases of the examples to those who will not be a reference. Specialized write a. Ha ha. But the Verilog.
Update : 2025-02-17 Size : 474kb Publisher : tupeng
[VHDL-FPGA-Verilog] dds DL : 0: 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
Update : 2025-02-17 Size : 186kb Publisher : 赵一
[VHDL-FPGA-Verilog] pll DL : 0: 用VERILOG语言实现的数字锁相环P-VERILOG language with the digital phase-locked loop PLL
Update : 2025-02-17 Size : 375kb Publisher : 叶少朋
[VHDL-FPGA-Verilog] pll DL : 0: 实现了pll功能，有利于初学者学习pll，采用文本编辑的，利用quartus ii 设计的-Achieved pll function, help beginners learn pll, using a text editor, using quartus ii Design
Update : 2025-02-17 Size : 211kb Publisher : ad
[Other] PLL_Analysis DL : 0: 关于锁相环（PLL）的经典教程，有相关matlab仿真程序的详细说明。来自国外的十分珍贵的资料。-With regard to phase-locked loop (PLL) of the classic tutorial matlab simulation program with relevant details. From abroad is very valuable information.
Update : 2025-02-17 Size : 64kb Publisher : yxyAlbert
[VHDL-FPGA-Verilog] 255 DL : 0: 全数字锁相环的Verilog源代码，经过仿真调试-All-digital PLL Verilog source code, through the simulation to debug
Update : 2025-02-17 Size : 151kb Publisher : 张文
[Software Engineering] PLL(pdf) DL : 0: 锁相环的设计方法介绍（PLL），可作为设计的参考。-Design method for PLL (PLL), can be used as a reference design.
Update : 2025-02-17 Size : 72kb Publisher : 李强
[VHDL-FPGA-Verilog] PLL_50MHz_to_12MHz DL : 0: Verilog HDL语言编写EP2C8Q208芯片PLL分频的简单程序，50MHz分频为12MHz-Verilog HDL language，EP2C8Q208 chip， PLL frequency of simple procedures, 50MHz to 12MHz frequency
Update : 2025-02-17 Size : 52kb Publisher : LM
[VHDL-FPGA-Verilog] PLL DL : 0: Phase locked loop(PLL) Verilog HDL code
Update : 2025-02-17 Size : 20kb Publisher : hr

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