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[VHDL-FPGA-Verilog] 128×16ram

Description: VHDL程序设计的RAM存储器，双端口，128×16比特-VHDL programming RAM memory, dual-port, 128 × 16 bits
Platform: | Size: 1024 | Author: petri | Hits:

[Other] ramchoice

Description: 多总线切换的VHDL代码。可用于多RAM的管理。-Multibus VHDL code switching. RAM can be used for multi-management.
Platform: | Size: 1024 | Author: 祝箭 | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: 介绍了viterbi译码器的编解码器的设计，包括decoder.v,encoder.v.control.v,ram.v等，压缩 包里面有pdf说明-Introduced a viterbi decoder codec design, including decoder.v, encoder.v.control.v, ram.v and so on, there are pdf compression package description
Platform: | Size: 62464 | Author: yaoyongshi | Hits:

[Compress-Decompress algrithms] fifo

Description: FIFO电路(first in，first out)，内部藏有１６ｂｉｔ×１６ｗｏｒｄ的Dual port RAM，依次读出已经写入的数据。因为不存在Address输入，所以请自行设计内藏的读写指针。由FIFO电路输出的EF信号(表示RAM内部的数据为空)和FF信号(表示RAM内部的数据为满)来表示RAM内部的状态，并且控制FIFO的输入信号WEN(写使能)和REN(读使能)。以及为了更好得控制FIFO电路，AEF(表示RAM内部的数据即将空)信号也同时输出。-FIFO circuit (first in, first out), internal possession of 16bit × 16word the Dual port RAM, in order to read out has been written into the data. Address because there is no input, so please read and write their own design containing the pointer. By the FIFO circuit output signal of the EF (express the internal data RAM is empty) and the FF signal (that the internal data RAM or above) to express the state of internal RAM and FIFO control of the input signal WEN (Write Enable) and REN ( Reading-enabled). As well as a control in order to better FIFO circuit, AEF (express the internal data RAM is about to air) signal output at the same time.
Platform: | Size: 1024 | Author: 史先生 | Hits:

[VHDL-FPGA-Verilog] Asynchronous_read_write_RAM

Description: Dual Port RAM Asynchronous Read/Write 经过modelsim仿真 -Dual Port RAM Asynchronous Read/Write through ModelSim Simulation
Platform: | Size: 1024 | Author: lianlianmao | Hits:

[VHDL-FPGA-Verilog] Synchronous_read_write_RAM

Description: Synchronous read write RAM verilog。经过modelsim se仿真。-Synchronous read write RAM verilog. Through simulation modelsim se.
Platform: | Size: 1024 | Author: lianlianmao | Hits:

[Other Embeded program] DDram

Description: 07全国大学生电子设计竞赛C题获奖作品FPGA外围接口双口RAM部分源码-07 National Undergraduate Electronic Design Contest winning entries C title peripheral interface FPGA dual-port RAM part of source
Platform: | Size: 1024 | Author: SRY | Hits:

[SCM] RAMbroden

Description: 基于proteus的51单片机的RAM扩展仿真-Based on the Proteus 51 MCU RAM expansion simulation
Platform: | Size: 23552 | Author: lianzi | Hits:

[DSP program] ex1_RAMTest

Description: DSP2812的外部RAM实验测试程序，很好用的！-DSP2812 external RAM experimental test procedure, good use!
Platform: | Size: 24576 | Author: 李静 | Hits:

[VHDL-FPGA-Verilog] acordwithram

Description: 一个牛人写的很快且不用状态机的动态RAM接口,VHDL编写-A cow were to write quickly and do not have the state machine dynamic RAM interface, VHDL prepared
Platform: | Size: 6144 | Author: john | Hits:

[VHDL-FPGA-Verilog] dul_ram(yk)

Description: 关于双口RAM的Verilog HDL源码-On the dual-port RAM in Verilog HDL source
Platform: | Size: 3072 | Author: 123 | Hits:

[SCM] DMA

Description: This example provides a description of how to use a DMA channel to transfer a word data buffer from memory (Flash) to memory (RAM). The dedicated DMA channel is configured to transfer once a time a 32 word data buffer stored as constant in the Flash memory to another buffer in the RAM memory. The received data are stored in the DST_Buffer. The DMA channel transfer complete interrupt is enabled to generate an interrupt at the end of the buffer transfer. As soon as the transfer is completed an interrupt is generated and in the DMA channel interrupt routine the transfer complete interrupt pending bit is cleared. The data counter is stored before and after the transfer to show that all data has been transfered. TransferStatus gives the data transfer status where it is PASSED if transmitted and received data are the same otherwise it is FAILED -This example provides a description of how to use a DMA channel to transfer a word data buffer from memory (Flash) to memory (RAM). The dedicated DMA channel is configured to transfer once a time a 32 word data bufferstored as constant in the Flash memory to another buffer in the RAM memory.The received data are stored in the DST_Buffer.The DMA channel transfer complete interrupt is enabled to generate an interrupt atthe end of the buffer transfer. As soon as the transfer is completed an interrupt isgenerated and in the DMA channel interrupt routine the transfer complete interrupt pending bit is cleared. The data counter is stored before and after the transfer to show that all data has beentransfered.TransferStatus gives the data transfer status where it is PASSED if transmitted and received data are the same otherwise it is FAILED
Platform: | Size: 507904 | Author: kz02bcxg | Hits:

[SCM] PIC-read-and-write-SPC3-ram

Description: PIC芯片读写SPC3寄存器的程序,PIC芯片不支持外部存储器扩展功能，通过软件编程，实现读写外部存储器功能。-PIC chip to read and write registers SPC3 procedures, PIC chip does not support external memory expansion capabilities, through software programming, to achieve read and write external memory function.
Platform: | Size: 4096 | Author: 陶学君 | Hits:

[SCM] 51RAM

Description: 单片机扩展片外RAM,用到的芯片有373,62256这里包涵了测试与串口调试等程序,可以用于扩展调试与串口通讯调试等-Single-chip expansion of chip RAM, the chips used here have 373,62256 includes the testing and debugging, such as serial procedures, can be used to expand the debugging and debug serial communication, etc.
Platform: | Size: 17408 | Author: 吕坤 | Hits:

[Linux-Unix] dev

Description: linux下 双口ram驱动程序 2.4.18-linux under the dual-port ram driver 2.4.18
Platform: | Size: 4096 | Author: 孙磊 | Hits:

[VHDL-FPGA-Verilog] Wave_ROM

Description: 基于RAm的FPGA实现DDS,有测试文件-Ram realize the FPGA-based DDS, have the test paper
Platform: | Size: 5120 | Author: xsj | Hits:

[Embeded-SCM Develop] fifov1

Description: FIFO（先进先出队列）通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。本FIFO的实现是利用 双口RAM 和读写地址产生模块来实现的.FIFO的接口信号包括异步的写时钟（wr_clk）和读时钟（rd_clk）、 与写时钟同步的写有效（wren）和写数据（wr_data） 、与读时钟同步的读有效（rden）和读数据（rd_data） 为了实现正确的读写和避免FIFO的上溢或下溢，给出与读时钟和写时钟分别同步的FIFO的空标志（empty）和 满标志（full）以禁止读写操作。-FIFO (FIFO queue) is usually used for data caching and asynchronous signal used to accommodate the frequency or phase differences. The realization of this FIFO is to use dual-port RAM and to read and write address generator module achieved. FIFO interface signals, including asynchronous write clock (wr_clk) and read clock (rd_clk), and write effectively write clock synchronization (wren) and write data (wr_data), clock synchronization and time effective reading (rden) and read data (rd_data) in order to realize the right to read and write and to avoid FIFO overflow or the underflow, is given with the time clock and write clock synchronization FIFO respectively empty signs (empty) and full logo (full) to prohibit the read and write operations.
Platform: | Size: 378880 | Author: lsg | Hits:

[SCM] f320f28335_FLASH_TO_RAM

Description: Copying Compiler Sections from Flash to RAM on the TMS320F28xxx DSCs 包括固件和说明-Copying Compiler Sections from Flash to RAM on the TMS320F28xxx DSCs include the firmware and instructions
Platform: | Size: 544768 | Author: caocao | Hits:

[assembly language] RAM

Description: 所有的ram资料，化了很长时间找的 大家多多指教 -Ram all information of a very long time to find the exhibitions of the U.S.
Platform: | Size: 247808 | Author: xgh | Hits:

[SCM] RAM

Description: 基于单片机AT89S52系统的一些测试程序，用C语言编写的，自己已经做实验验证过了-Based on MCU AT89S52 system testing procedures, using C language, they have to do the experiment verified the
Platform: | Size: 13312 | Author: 刘玉领 | Hits:
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