Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - RS232 to pc fpga

Search list

[VHDL-FPGA-Verilog] RS232capture

Description: This approach, we feel, came very close to obtaining an image from the camera OV7620. Before we tried to capture a camera signal, we successfully transferred a test image from the FPGA s onboard RAM modules through RS232 to the PC program. This file do it.
Platform: | Size: 39936 | Author: Joelmir J Lopes | Hits:

[VHDL-FPGA-Verilog] RS232

Description: 基于Xilinx Spartan3E的RS232驱动，能够实现FPGA与PC得通信-Xilinx Spartan3E based on the RS232 driver, to achieve a FPGA and PC communication
Platform: | Size: 512000 | Author: darkblue | Hits:

[VHDL-FPGA-Verilog] XC4VLX60MB_Lab3_RS232_ISE91

Description: FPGA design, In addition to logic design, the future also can be SOC (System On Chip) approach to achieve a future A complete design system, so XC4VLX60 the board design includes RS232 and LCD surrounding the design, this experiment will Super terminal RS232 and PC connectivity for asynchronous data transmission, as RS232 verification and practice.-FPGA design, In addition to logic design, the future also can be SOC (System On Chip) approach to achieve a future A complete design system, so XC4VLX60 the board design includes RS232 and LCD surrounding the design, this experiment will Super terminal RS232 and PC connectivity for asynchronous data transmission, as RS232 verification and practice.
Platform: | Size: 498688 | Author: vkiy | Hits:

[VHDL-FPGA-Verilog] rs232

Description: 本设计是PC和FPGA的串口通信的程序，用的是VERILOG语言，调试成功，用户可根据自己的项目稍作改动。-The design is a PC and the FPGA' s serial communication procedures, using a VERILOG language, debugged, the user can make a little change according to their own projects.
Platform: | Size: 2048 | Author: 陆景鹏 | Hits:

[VHDL-FPGA-Verilog] miniuart2

Description: 用ＶＨＤＬ在CPLD/FPGA上实现与PC机的RS232通信-This UART (Universal Asynchronous Receiver Transmitter) is designed to make an interface between a RS232 line and a wishbone bus, or a microcontroller, or an IP core. It works fine connected to the serial port of a PC for data exchange with custom electronic. It was built in the perspective to be very small, but efficient. It had to fit in a small FPGA. It is not suited to interface a modem as there is no control handshaking (CTS/RTS). It integrate two separate clocks, one for wishbone bus, the other for bitstream generation. This has the advantage to let the user bring his own desired frequency for the baudrate.
Platform: | Size: 2588672 | Author: 李涛 | Hits:

[Com Port] FPGA-RS232-verilog

Description: fpga上的串口驱动程序，包括接收主机来的数据（deserial）和发送由FPGA产生的数据(serial).该程序的调试需要借助串口调试助手-serial port driver on the fpga, including the receiving host to the data (deserial) and send the data generated by the FPGA (serial) to pc. The program needs the serial debug debugging assistant
Platform: | Size: 500736 | Author: yvaine | Hits:

[VHDL-FPGA-Verilog] A-Simplified-VHDL-UART

Description: In embedded systems, the processor that we choose for our design may not come with built-in peripherals. Therefore, designers will have to implement these devices in hardware keeping in mind that they will need to interface to the processor. In this lab we will design a simplified UART (Universal Asynchronous Reciever Transmitter) in VHDL and download it to the FPGA on the XS40 baord. Serial communication is often used either to control or to receive data from an embedded microprocessor. Serial communication is a form of I/O in which the bits of a byte begin transferred appear one after the other in a timed sequence on a single wire. Serial communication has become the standard for intercomputer communication. In this lab, we ll try to build a serial link between 8051 and PC using RS232.
Platform: | Size: 374784 | Author: mezzich | Hits:

[VHDL-FPGA-Verilog] uart1

Description: vhdl uart module. this file is used to transfer programs frm fpga xilinx spartam 3e kit to desktop pc through rs232 serial port.
Platform: | Size: 282624 | Author: pingakshya | Hits:

[VHDL-FPGA-Verilog] my_uart1_VERILOG_using-PLL

Description: Verilog uart example, RS232的Verilog例子。PC 发送一个字节（byte）到板子（FPGA），板子回发一个(byte+1).例子简洁，有注释。用到PLL，而且有3：2次数据采用-Verilog uart example，Verilog RS232 example，it s easy to understand, PC send 1 Byte RS232 code to FPGA, FPGA return 1 tht code，but Byte+1， Using PLL
Platform: | Size: 506880 | Author: 林端 | Hits:

[VHDL-FPGA-Verilog] RS232_COMPLETE

Description: Communication RS232 between Hyperterminal PC to FPGA Spartan 3E
Platform: | Size: 472064 | Author: MarceloBG | Hits:

[Other Embeded program] MyC2Board_RS232_Test

Description: 这是一个Altera FPGA NIOS II RS232通讯程序。 在Quartus II工程中，用Qsys建立了一个NIOS II为核心的CPU系统，并挂接了一个RS232接口。 在software目录下，有三个工程，一个是用C++类包装的RS232类的Eclipse工程，一个是不用C++类包装的Eclipse工程，还有一个是用VC++2008编写的RS232测试工程。 VC++2008编写的工程运行在PC机上，与FPGA中的NIOS II通讯。 这个实验的主要目的是编写一个通用RS232类，这个类即可以用于NIOS II，又可以用于PC机，是一个可重用的RS232类；我们用这个类开发了不少以PC为控制平台，FPGA为硬件控制器的测试系统。 -This is an Altera FPGA NIOS II RS232 communication project. In the Quartus II project, there is a NIOS II CPU with RS232. In the Software directory, there are 3 projects. First one is an Eclipse Project with C++ RS232 Class. Second one is an Eclipse Project with C RS232.h. Other one is a VC++2008 Project with C++ RS232 Class. The purpose of this project is to write a RS232 Class use on any system needed RS232 communication. The RS232 Class not only use on NIOS II, but also use on PC. We used this RS232 Class on many Test Systems with PC and FPGA
Platform: | Size: 13864960 | Author: li hui xian | Hits:

[VHDL-FPGA-Verilog] UART

Description: （1）在FPGA上设计UART接收模块实现从PC接收串口数据(RS232串口通信)； （2）在FPGA上设计UART发送模块，把从PC接收的数据的16进制值加1再发送给PC； -(1) Design UART receiver module receives serial data (RS232 serial communication) the PC to the FPGA (2) Design UART transmit module on FPGA, the hexadecimal value of the data received the PC plus one re-sent to the PC
Platform: | Size: 576512 | Author: shan | Hits:

[Other] uart_2_pc

Description: 实现FPGA和PC通过串口传输数据，已经通过验证，可以结合自己的设计直接拿来用(ealize FPGA and PC to transmit data through serial port)
Platform: | Size: 1024 | Author: 紫木檀香雪 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 此上传文件实现的功能就是FPGA里实现从PC接收数据，然后把接收到的数据发回去。 使用的是串口UART协议进行收发数据。(The function of this upload file is to receive data from PC in FPGA and send back the received data.The serial port UART protocol is used to receive and receive data.)
Platform: | Size: 1649664 | Author: 木子桶 | Hits:

CodeBus www.codebus.net