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[Other resource] mt48lc8m16a2

Description: sdram的行为级模拟模块,可以模拟一个sdram,用于仿真对sdram的控制.-sdram behavioral simulation module can simulate a sdram. Simulation for the control of sdram.
Platform: | Size: 6652 | Author: hxwf801 | Hits:

[VHDL-FPGA-Verilog] mt48lc8m16a2

Description: sdram的行为级模拟模块,可以模拟一个sdram,用于仿真对sdram的控制.-sdram behavioral simulation module can simulate a sdram. Simulation for the control of sdram.
Platform: | Size: 6144 | Author: hxwf801 | Hits:

[VHDL-FPGA-Verilog] control_interface

Description: SDRAM控制器Verilog员代码，控制接口模块，完成和顶层模块的控制命令的传递-SDRAM controller member Verilog code control interface module, Top module and complete the transfer of control orders
Platform: | Size: 3072 | Author: 陈建勇 | Hits:

[VHDL-FPGA-Verilog] Commandinterface

Description: SDRAM控制器Verilog员代码，命令生成模块，完成SDRAM控制接口命令的生成-SDRAM controller member Verilog code, order generation module, SDRAM interface complete control orders Generation
Platform: | Size: 7168 | Author: 陈建勇 | Hits:

[Program doc] FPGA

Description: SDRAM控制模块；图象采集系统说明性稳当；DSP图象采集系统。SDRAM作为存储器。-SDRAM control module image acquisition system illustrative trustworthy DSP image acquisition system. SDRAM as the memory.
Platform: | Size: 179200 | Author: yan | Hits:

[Software Engineering] FPGA_SDR_Sdram_LED

Description: 针对主控制板上存储器(SRAM) 存储的数据量小和最高频率低的情况,提出了基于SDR Sdram(同步动态RAM) 作为主存储器的LED 显示系统的研究。在实验中,使用了现场可编程门阵列( FPGA) 来实现各模块的逻辑功能。最终实现了对L ED 显示屏的控制,并且一块主控制板最大限度的控制了256 ×128 个像素点,基于相同条件,比静态内存控制的面积大了一倍,验证了动态内存核[7 ]的实用性。-For the main control board memory (SRAM) a small amount of stored data and the highest frequency of low, based on SDR Sdram (Synchronous Dynamic RAM) as the main memory of the LED display systems. In the experiment, the use of field programmable gate array (FPGA) to realize the logic function of each module. The eventual realization of L ED display control, and a master control panel to maximize the control of the 256 × 128 pixels point, based on the same conditions than the static memory control area has doubled, to verify the dynamic memory of nuclear [7 ] the practicality.
Platform: | Size: 510976 | Author: 郑宏超 | Hits:

[Other] sdram_vhdl_lattice

Description: sdram的控制程序，程序分为控制端口模块、时钟模块、数据传输模块及刷新等模块-sdram control procedures, process control port is divided into modules, clock modules, data transfer module and refresh modules
Platform: | Size: 369664 | Author: 邢雷 | Hits:

[VHDL-FPGA-Verilog] SDRAMcontrollerdesignl

Description: The SDRAM Controller module makes you control SDRAM conveniently with easy interface input type
Platform: | Size: 411648 | Author: phwer01 | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: 对SDRAM的介绍非常详细，里面有很多对SDRAM的程序控制模块的设计。-Very detailed presentation on the SDRAM, which has many of the SDRAM of the process control module.
Platform: | Size: 23523328 | Author: 魏大胜 | Hits:

[VHDL-FPGA-Verilog] sdram_hr_hw_4port

Description: FPGA控制SDRAM的源程序,SDRAM控制起来比较麻烦,时序复杂,本程序将其封装了一个模块,可以方便地调用.-FPGA to control the source of SDRAM, SDRAM control is too much trouble, the timing complexity of the procedure to package a module, you can easily call.
Platform: | Size: 2339840 | Author: 刘成岩 | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: 在ISE环境下对SDRAM(异步动态存储器)的控制模块设计。-In the ISE environment of SDRAM ( asynchronous DRAM ) control module design.
Platform: | Size: 12853248 | Author: 陈拓 | Hits:

[DSP program] DSPRobotPVision(3)

Description: 一些关于机器人方面的资料，包括：DSP片外高速海量SDRAM存储系统设计、机器人视觉（Robot Vision）简介、基于DSP的爬行机器人主控制模块设计履带式管道清洁机器人嵌入式控制与通信系统的研究、线阵CCD图像传感器驱动电路的设计-Information about the robots, including: high-speed mass DSP-chip SDRAM memory system design, robot vision (Robot Vision) Profile-based DSP-crawling robot main control module is designed crawler pipeline cleaning robot embedded control and communications systems, linear CCD image sensor drive circuit design
Platform: | Size: 3864576 | Author: liumei | Hits:

[Other] sdram_mdl

Description: SDRAM的verilog程序控制模块，希望对大家有帮助-SDRAM verilog program control module, we want to help
Platform: | Size: 2196480 | Author: yxm | Hits:

[VHDL-FPGA-Verilog] vhdl-Language-routine-highlights

Description: 工程中常用的VHDL控制模块，包括三态门，SDRAM，FIFO，PLL，RAM，FIlter等模块，非常实用的工程代码-Control module of VHDL is commonly used in engineering, including the tri-state gate, SDRAM, FIFO, PLL, RAM, FIlter module, very practical engineering code
Platform: | Size: 291840 | Author: shujian | Hits:

[MPI] SDRAM_FPGA

Description: 这个是SDRAM的控制程序，包括包括UART和FIFO模块，适合FPGA开发人员看，也适合初学者学习。-This is the SDRAM control procedures, including including UART and FIFO module, suitable for FPGA developers look, but also suitable for beginners to learn.
Platform: | Size: 2957312 | Author: zhangquanling | Hits:

[VHDL-FPGA-Verilog] sdram

Description: 本程序在Quartus ii 环境中开发设计了SDRAM的控制模块，功能齐全正确，能正确对SDRAM进行读写-This procedure in Quartus ii environment development and design of SDRAM control module, complete functions correctly, the SDRAM read and write correctly
Platform: | Size: 4752384 | Author: zhu | Hits:

[Other] 0801sdram_burst8_better

Description: sdram burst=8控制模块,比较好的实现控制-sdram burst =8 control module，it is good for you to use it
Platform: | Size: 18432 | Author: 樊满 | Hits:

[VHDL-FPGA-Verilog] SDRAM_Verilog

Description: 本源码由Verilog语言编写，用硬件实现SDRAM的读写和存储数据功能，包括SDRAM的控制模块、初始化模块、读写模块等！-The source the Verilog language, implemented in hardware SDRAM read and write and store data, including SDRAM control module, initialization module, reader module, etc!
Platform: | Size: 3072 | Author: zhanglong | Hits:

[Other] 11_sdram_test

Description: module sdram_test( input clk_50m, input reset_n, //sdram control output S_CLK, //sdram clock output S_CKE, //sdram clock enable output S_NCS, //sdram chip select output S_NWE, //sdram write enable output S_NCAS, //sdram column address strobe output S_NRAS, //sdram row address strobe output [1:0] S_DQM, //sdram data enable output [1:0] S_BA, //sdram bank address output [12:0] S_A, //sdram address inout [15:0] S_DB //sdram data ) -module sdram_test( input clk_50m, input reset_n, //sdram control output S_CLK, //sdram clock output S_CKE, //sdram clock enable output S_NCS, //sdram chip select output S_NWE, //sdram write enable output S_NCAS, //sdram column address strobe output S_NRAS, //sdram row address strobe output [1:0] S_DQM, //sdram data enable output [1:0] S_BA, //sdram bank address output [12:0] S_A, //sdram address inout [15:0] S_DB //sdram data )
Platform: | Size: 2787328 | Author: Wen Jun Ying | Hits:

[VHDL-FPGA-Verilog] sdram

Description: sdram的控制程序，以及相关的testbench(sdram control module)
Platform: | Size: 128000 | Author: 大地2020 | Hits:
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