Description: SPI总线硬件描述语言Verilog下的实现，含主模式和从模式的实现，经过仿真验证，可作为一个单独的模块使用-SPI bus under the Verilog hardware description language to achieve with the main mode and slave mode realization, through simulation, can be used as a separate module uses Platform: |
Size: 5120 |
Author:高兵 |
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Description: mcu与cpld之间spi接口程序，mcu为master，cpld用verilog写成slave模块-mcu with spi interface program between the CPLD, mcu for the master, cpld written using Verilog slave module Platform: |
Size: 110592 |
Author:叶灿 |
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Description: This is a verilog code used oversampled
clock to implement SPI slave. Also include C code for a ARM processor
as the SPI master-This is a verilog code used oversampled
clock to implement SPI slave Platform: |
Size: 1024 |
Author:johnl |
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Description: 数字通信原理 曹志刚版的SPI总线硬件描述语言Verilog下的实现，含主模式和从模式的实现，经过仿真验证，可作为一个单独的模块使用--Digital Communication Principles of CAO Zhi-gang version of the SPI bus, under the Verilog hardware description language implementation, including Master mode and slave mode of implementation, through the simulation can be used as a separate module-- Platform: |
Size: 8550400 |
Author:liusen |
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Description: 一个强大的符合SPI规范的VHDL/Verilog源码文件，传输模式和时钟相位均可以指定，采用同步时钟设计，可以工作在很高的频率下。支持主机及从机模式，强烈推荐使用！-A strong line with SPI standard VHDL/Verilog source files, transfer mode, and clock phase are to specify, using synchronous clock design can work in very high frequency. Support the host and slave mode, strongly recommended! Platform: |
Size: 13312 |
Author:中国 |
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Description: SPI（Serial Peripheral Interface，串行外设接口）是Motorola公司提出的一种同步串行数据传输标准，是一种高速的，全双工，同步的通信总线，在很多器件中被广泛应用。
SPI相关缩写
SS: Slave Select，选中从设备，片选。
CKPOL (Clock Polarity) = CPOL = POL = Polarity = （时钟）极性
CKPHA (Clock Phase) = CPHA = PHA = Phase = （时钟）相位
SCK = SCLK = SCL = SPI的时钟（Serial Clock）
Edge = 边沿，即时钟电平变化的时刻，即上升沿(rising edge)或者下降沿(falling edge)。
对于一个时钟周期内，有两个edge，分别称为：
Leading edge = 前一个边沿 = 第一个边沿，对于开始电压是1，那么就是1变成0的时候，对于开始电压是0，那么就是0变成1的时候；
Trailing edge = 后一个边沿 = 第二个边沿，对于开始电压是1，那么就是0变成1的时候（即在第一次1变成0之后，才可能有后面的0变成1），对于开始电压是0，那么就是1变成0的时候；(SPI (Serial Peripheral Interface, serial peripheral interface) is a synchronous serial data transmission standard put forward by Motorola company, is a high-speed, full duplex, synchronous communication bus, is widely used in many devices.
SPI related abbreviations
SS: Slave Select, selected from the device, chip select.
CKPOL (Clock, Polarity) = CPOL = POL = Polarity = (clock) polarity
CKPHA (Clock, Phase) = CPHA = PHA = Phase = (clock) phase
SCK = SCLK = SCL = SPI clock (Serial, Clock)
Edge = edge, instant clock, level change time, i.e. rising edge (rising, edge) or falling edge (falling, edge).
For a clock cycle, there are two edge, respectively:
Leading edge = front edge = first edge, for start voltage is 1, then 1 is 0, for start voltage is 0, then 0 is 1;
Trailing = edge = second after an edge edge, the start voltage is 1, it is 0 to 1 of the time (that is, after the first 1 to 0, it may be behind the 0 to 1), the start voltage is 0, it is 1 to 0 times;) Platform: |
Size: 6144 |
Author:helimpopo
|
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