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[VHDL-FPGA-Verilog] bunchcombinechange

Description: Verilog源代码,实现串并转换，学Verilog的不错的基本例程-Verilog source code, realize SERDES, learning Verilog good basic routines
Platform: | Size: 114688 | Author: 3060421006 | Hits:

[Other] MIIinterface

Description: MII接口1转2处理，可以实现在serdes上方便传输MII。-MII interface 1 to 2 treatment can be achieved in the serdes to facilitate transmission MII.
Platform: | Size: 9216 | Author: BrivaMa | Hits:

[VHDL-FPGA-Verilog] serial

Description: 串行口数据传输实验，vhdl源代码，完成信号发生，串并转换，检测电路-Serial port data transmission experiment, vhdl source code, complete the signal occurred, SERDES, detection circuit
Platform: | Size: 1024 | Author: yew | Hits:

[Communication] Design_of_a_6.25_Gbps_Backplane_SerDes_with_TOP-do

Description: SerDes自顶向下的设计方法流程，包括接收机、发射机、均衡技术、时钟恢复技术-SerDes top-down design methodology process, including receivers, transmitters, equalization, clock recovery techniques
Platform: | Size: 592896 | Author: 周明珠 | Hits:

[Software Engineering] Equalization_in_high-speed_communication_systems.r

Description: 高速通信系统中均衡器的几种结构说明与比较，对设计SerDes的朋友有帮助-High-speed communications systems equalizer description and comparison of several structures, the design SerDes friends help
Platform: | Size: 837632 | Author: 周明珠 | Hits:

[MPI] readme_vhd

Description: VHDL串并转换源程序，可以实现信号在串行和并行间的转换。-SERDES VHDL source code, you can achieve signal at between serial and parallel conversion.
Platform: | Size: 1024 | Author: kimli | Hits:

[VHDL-FPGA-Verilog] LVDS_Serdes_list_FPGA1

Description: FPGA之间的LVDS传输，采用serdes接口，传输速率达到400m-LVDS transmission between the FPGA using serdes interface, transfer rate up to 400m
Platform: | Size: 14338048 | Author: linpingping | Hits:

[VHDL-FPGA-Verilog] 74595

Description: 串并转换仿真，内有详细说明和仿真波形，能够成功运行-SERDES simulation
Platform: | Size: 1252352 | Author: liuchao | Hits:

[Program doc] StratixGX

Description: Stratix GX器件在SDH宽带交换中的应用-Stratix SDH serdes
Platform: | Size: 28672 | Author: fnd | Hits:

[VHDL-FPGA-Verilog] auk_sdsdi

Description: 用于FPGA设计的代码（Verilog代码），在FPGA设计中的高速串并转换，时钟提取，对齐处理等功能-for FPGA design ,written by Verilog HDL the functions include SERDES , CDR and so on
Platform: | Size: 229376 | Author: 龙珠 | Hits:

[VHDL-FPGA-Verilog] MAIN_RX_V10

Description: 8路视频光端机 接收侧 VHDL源码，使用了千兆以太网SERDES芯片，基于TBI接口的PCM视频传输。-8-Channel Video Optical Receiver side of VHDL source code, using the Gigabit Ethernet SERDES chip, based on the TBI interface PCM video transmission.
Platform: | Size: 1088512 | Author: tr | Hits:

[VHDL-FPGA-Verilog] TX

Description: 1路视频光端机的发射端，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES-The launch of a video PDH client, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
Platform: | Size: 103424 | Author: tr | Hits:

[VHDL-FPGA-Verilog] RX

Description: 1路视频光端机的接收端，VHDL源码，使用全FPGA芯片的硬件，内建解帧、时钟、DESERDES-PDH a video of the receiving end, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
Platform: | Size: 104448 | Author: tr | Hits:

[VHDL-FPGA-Verilog] F7-2VT-1DR

Description: 2路视频光端机的，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES-2-way video PDH' s, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
Platform: | Size: 461824 | Author: tr | Hits:

[Program doc] Multi_Gigabit_transceiver

Description: A Multi-Gigabit Transceiver (MGT) is a SerDes capable of operating at serial bit rates above 1 Gigabit/second. MGTs are used increasingly for data communications because they can run over longer distances, use fewer wires, and thus have lower costs than parallel interfaces with equivalent data throughput.
Platform: | Size: 466944 | Author: cidadeus | Hits:

[VHDL-FPGA-Verilog] SERDES

Description: 基于Verilog的串并转换器的设计与实现，采用两种不同的方案来实现串并和并串转换的功能，并用ISE软件仿真以及chipscope的调试-Verilog-based serial and parallel converter design and implementation of two different programs to achieve the string and and and string conversion functions, and use the ISE software simulation and debugging chipscope
Platform: | Size: 785408 | Author: 陈凯 | Hits:

[VHDL-FPGA-Verilog] SerDes-Architectures-and-Applications

Description: 关于lvds四种串行解串器的架构和应用的详细介绍和讨论，非常适合初学者使用-About lvds of four serial SerDes architecture and applications presented and discussed in detail, ideal for beginners
Platform: | Size: 612352 | Author: kevin | Hits:

[Software Engineering] designcon2004_serdes

Description: DESIGN CON SERDES PDF DOCUMENT
Platform: | Size: 504832 | Author: CDVLSI | Hits:

[VHDL-FPGA-Verilog] DK-ECP3-SERDES-010

Description: 为verilog 的SERDES 使用程序。可以实现高速串行接口数据通信，时钟还原。-Verilog program for the use of the SERDES. For high-speed serial interface data communications, clock restoration.
Platform: | Size: 6337536 | Author: fpga_cn | Hits:

[VHDL-FPGA-Verilog] 8b10btest

Description: lattice fpga serdes接口程序-lattice fpga serdes interface program
Platform: | Size: 1024 | Author: yufei | Hits:
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