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[Other resource] Full_Adder

Description: 全加器的VHDL_CODE和TEST_BENCH 無須解壓縮密碼-full adder and the VHDL_CODE TEST_BENCH not extract passwords
Platform: | Size: 1428 | Author: 韓堇 | Hits:

[Other resource] fpu_v18

Description: <Floating Point Unit Core> fpupack.vhd pre_norm_addsub.vhd addsub_28.vhd post_norm_addsub.vhd pre_norm_mul.vhd mul_24.vhd vcom serial_mul.vhd post_norm_mul.vhd pre_norm_div.vhd serial_div.vhd post_norm_div.vhd pre_norm_sqrt.vhd sqrt.vhd post_norm_sqrt.vhd comppack.vhd fpu.vhd ***For simulation **** To run the simulation read readme.txt in folder test_bench.
Platform: | Size: 477666 | Author: 陈朋 | Hits:

[Other resource] Test_Bench

Description: 8篇测试向量(Test_Bench)和波形产生的例子(VHDL语言，开发环境：FPGA)
Platform: | Size: 12154 | Author: 11 | Hits:

[Other resource] Test_Bench

Description: 波形发生器.经典双进程状态机.相应加法器的测试向量
Platform: | Size: 6623 | Author: 周斌 | Hits:

[VHDL-FPGA-Verilog] Full_Adder

Description: 全加器的VHDL_CODE和TEST_BENCH 無須解壓縮密碼-full adder and the VHDL_CODE TEST_BENCH not extract passwords
Platform: | Size: 1024 | Author: 韓堇 | Hits:

[VHDL-FPGA-Verilog] fpu_v18

Description: <Floating Point Unit Core> fpupack.vhd pre_norm_addsub.vhd addsub_28.vhd post_norm_addsub.vhd pre_norm_mul.vhd mul_24.vhd vcom serial_mul.vhd post_norm_mul.vhd pre_norm_div.vhd serial_div.vhd post_norm_div.vhd pre_norm_sqrt.vhd sqrt.vhd post_norm_sqrt.vhd comppack.vhd fpu.vhd ***For simulation **** To run the simulation read readme.txt in folder test_bench.-<Floating Point Unit Core> fpupack.vhdpre_norm_addsub.vhdaddsub_28.vhdpost_norm_addsub.vhdpre_norm_mul.vhdmul_24.vhdvcom serial_mul.vhdpost_norm_mul.vhdpre_norm_div.vhdserial_div.vhdpost_norm_div.vhdpre_norm_sqrt.vhdsqrt.vhdpost_norm_sqrt.vhdcomppack.vhdfpu.vhd*** For simulation**** To run the simulation read readme.txt in folder test_bench.
Platform: | Size: 477184 | Author: 陈朋 | Hits:

[VHDL-FPGA-Verilog] Test_Bench

Description: 8篇测试向量(Test_Bench)和波形产生的例子(VHDL语言，开发环境：FPGA)-Eight test vectors (Test_Bench) and example of waveform generator (VHDL language, development environment: FPGA)
Platform: | Size: 12288 | Author: 11 | Hits:

[VHDL-FPGA-Verilog] Test_Bench

Description: 波形发生器.经典双进程状态机.相应加法器的测试向量-Waveform generator. Classic dual-process state machine. Corresponding adder test bench
Platform: | Size: 6144 | Author: 周斌 | Hits:

[Com Port] UART

Description: 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
Platform: | Size: 9216 | Author: 李佳 | Hits:

[Embeded-SCM Develop] test_bench

Description: test bench for booth multiplier
Platform: | Size: 1024 | Author: judy | Hits:

[VHDL-FPGA-Verilog] test_bench

Description: Test benching in VHDL
Platform: | Size: 322560 | Author: ali | Hits:

[VHDL-FPGA-Verilog] sdram

Description: 程序说明: 本次实验控制开发板上面的SDRAM完成读写功能。 先向SDRAM里面写数据，然后再将数据读出来做比较，如果不匹配就通过LED变亮显示出来，如果一致，LED就不亮。 part1是使用Modelsim仿真的工程 part2是在开发斑上面验证的工程 目录说明: part1: part1_32是4m32SDRAM的仿真工程 part1_16是4m16SDRAM的仿真工程 \model文件夹里面是仿真模型 \rtl文件夹里面是源文件 \sim文件夹里面是仿真工程 \test_bench文件夹里面是测试文件 \wave文件夹里面是仿真波形 -Procedure Note: In this experiment, control development board to complete the above SDRAM read and write capabilities. SDRAM write data inside first and then read out the data to compare, if you do not match on the adoption of LED variable light display, if agreed, LED does not light. part1 is to use Modelsim simulation project part2 the top spot verification in the development of the project directory Description: part1: part1_32 is 4m32SDRAM simulation project part1_16 is 4m16SDRAM simulation works \ model folder, which is a simulation model \ rtl folder, which is the source file \ sim is a simulation project inside the folder \ test_bench folder which is a test file \ wave inside the folder is a simulation waveform
Platform: | Size: 779264 | Author: 军军 | Hits:

[VHDL-FPGA-Verilog] dual_RAM

Description: vhdl语言编写的双口ram及testbench,模块可以在modelsim里进行时序和功能仿真。-vhdl language of the dual-port ram, and testbench, modules, conducted in the modelsim timing and functional simulation.
Platform: | Size: 1024 | Author: 易凯 | Hits:

[VHDL-FPGA-Verilog] FIFO_TD

Description: FIFO的VHDL测试程序,在Modelsim下完全可以运行-The test_bench of fifo
Platform: | Size: 2048 | Author: 三木 | Hits:

[Embeded-SCM Develop] test_bench

Description: test bench for booth multiplier
Platform: | Size: 1024 | Author: ectivehe | Hits:

[Software Engineering] Modelsim_and_Test_Bench

Description: 详细介绍了Modelsim软件的使用方法，图文并茂，以及介绍了Test_Bench的编写规则和方法。-Introduces the method of using Modelsim software, illustrations, and introduces the rules and methods of Test_Bench.
Platform: | Size: 400384 | Author: ft | Hits:

[VHDL-FPGA-Verilog] div10_test

Description: 10分频Verilog代码，以及test_bench仿真代码。-DIV10 Verilog
Platform: | Size: 1825792 | Author: ouhongshi | Hits:

[Program doc] viterbi_imp_de_tb_test

Description: This a Viterbi Decoding Algorithm Trace Back algorithm. Very useful for decoding in communication channel. the Survivor path is taken to be four bits. We have taken 4 states here. The branch metrics are calculates accordingly.All the signals have been tested here.The test_bench module is also included. We have taken care of the fact that encoded output goes continuously here.-This is a Viterbi Decoding Algorithm Trace Back algorithm. Very useful for decoding in communication channel. the Survivor path is taken to be four bits. We have taken 4 states here. The branch metrics are calculates accordingly.All the signals have been tested here.The test_bench module is also included. We have taken care of the fact that encoded output goes continuously here.
Platform: | Size: 5120 | Author: alo | Hits:

[VHDL-FPGA-Verilog] filtra-lowpass

Description: this a lowpass filtre in VHDL code with a test_bench you will find some specifications of the FIR-this is a lowpass filtre in VHDL code with a test_bench you will find some specifications of the FIR
Platform: | Size: 5120 | Author: mortadha | Hits:

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