Search - UART FPGA verilog

[Other Embeded program] pcit32_verilog_lattice

Description: 本文件是pci的verilog源代码程序-pci the Verilog source code procedures
Platform: | Size: 430080 | Author: 王立华 | Hits:

[VHDL-FPGA-Verilog] Altera_uart_Verilog

Description: FPGA/CPLD应用,uart的Verilog HDL原码-FPGA/CPLD applications, UART Verilog HDL source
Platform: | Size: 10240 | Author: cyberworm | Hits:

[VHDL-FPGA-Verilog] u-uart

Description: 一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code
Platform: | Size: 5120 | Author: 李文文 | Hits:

[VHDL-FPGA-Verilog] Fusion_UART

Description: UART实验Verilog HDL代码，用于FPGA-UART experimental Verilog HDL code for FPGA
Platform: | Size: 3072 | Author: 张猛蛟 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 串口通讯 verilog CPLD EPM1270 源代码-Serial Communication verilog CPLDEPM1270 source code
Platform: | Size: 56320 | Author: 韩思贤 | Hits:

[VHDL-FPGA-Verilog] fpga_uartrw

Description: FPGA的uart控制器的verilog源程序，在cyclone II EP2C8Q208上调试运行成功-FPGA s UART controller Verilog source code, in cyclone II EP2C8Q208 debugging run successfully
Platform: | Size: 55296 | Author: 蒋斌斌 | Hits:

[Industry research] UART_DESIGN

Description: The use of hardware description languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level description not only increases design productivity, but also provides unique advantages for design verification. The most dominant HDLs today are Verilog and VHDL. This application note illustrates the use of Verilog in the design and verification of a digital UART (Universal Asynchronous Receiver & Transmitter).
Platform: | Size: 141312 | Author: ltrko9kd | Hits:

[Software Engineering] xapp341

Description: verilog uart for spartan 3 fpga, its great
Platform: | Size: 21504 | Author: kashif | Hits:

[Com Port] uart

Description: 串口通讯 PC发送FPGA接受后回传 verilog语言-uart verilog
Platform: | Size: 3072 | Author: 赵云 | Hits:

[Other Embeded program] uart

Description: fpga 串行口接收和发送程序，采用verilong语言编写-fpga uart ，receive and send include writed by verilog language
Platform: | Size: 371712 | Author: james | Hits:

[VHDL-FPGA-Verilog] UART

Description: 使用Quartus ii软件，编程语言为Verilog语言，实现UART通信协议，FPGA的时钟信号为50MHz-Using the Quartus ii software, programming languages Verilog, UART communication protocol implementation, FPGA 50MHz clock signal
Platform: | Size: 1435648 | Author: 冰色火焰 | Hits:

[VHDL-FPGA-Verilog] UART

Description: FPGA的UART程序，非常好的，讲解详细，我当初看了好多都看不懂，看了这个以后终于明白-FPGA' s UART program, very good, detailed explanation, I had read a lot have not read, finally realized after reading this
Platform: | Size: 276480 | Author: xuxing | Hits:

[VHDL-FPGA-Verilog] UART

Description: Verilog HDL写的实现ＵＡＲＴ收发程序-Realization of Verilog HDL UART receive written procedures
Platform: | Size: 709632 | Author: xiong | Hits:

[Com Port] FPGA-RS232-verilog

Description: fpga上的串口驱动程序，包括接收主机来的数据（deserial）和发送由FPGA产生的数据(serial).该程序的调试需要借助串口调试助手-serial port driver on the fpga, including the receiving host to the data (deserial) and send the data generated by the FPGA (serial) to pc. The program needs the serial debug debugging assistant
Platform: | Size: 500736 | Author: yvaine | Hits:

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[Other Embeded program] pcit32_verilog_lattice

[VHDL-FPGA-Verilog] Altera_uart_Verilog

[VHDL-FPGA-Verilog] u-uart

[VHDL-FPGA-Verilog] Fusion_UART

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] fpga_uartrw

[Industry research] UART_DESIGN

[Software Engineering] xapp341

[Com Port] uart

[Other Embeded program] uart

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] UART

[Com Port] FPGA-RS232-verilog

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] Uart

[VHDL-FPGA-Verilog] UART-Altera

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] uart

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