Description: 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。-Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to start bit, 8 data bits, 1 stop bit, no parity. UART and send its own two FIFO buffer occupancy is very small FPGA. Platform: |
Size: 876544 |
Author:张键 |
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Description: 是使用ISE实现UART通信功能，可以提高你的FPGA能力。-Is to use the ISE implementation UART communication can improve the ability of your FPGA. Platform: |
Size: 18432 |
Author:dengfeng |
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Description: 为增加系统稳定性，减小电路板面积，提出一种基于FPGA的异步串行口IP核设计。该设计使用VHDL硬件描述语言时接收和发送模块在Xilinx ISE环境下设计与仿真。最后在FPGA上嵌入UART IP核实现电路的异步串行通信功能。该IP核具有模块化、兼容性和可配置性，可根据需要实现功能的升级、扩充和裁减。-In order to increase system stability, reduce board space, presents a FPGA-based asynchronous serial port IP-core design. The design using the VHDL hardware description language to receive and transmit modules in Xilinx ISE design and simulation environment. Finally, embedded UART IP core on the FPGA circuit implementation of the asynchronous serial communications. The IP core has a modular, compatibility and configurability, can achieve the functionality needed upgrade, expansion and reduction. Platform: |
Size: 215040 |
Author:jalon |
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Description: UART FPGA实现过程文档说明，及VERILOG HDL 代码，希望能帮助有需要的人，-UART FPGA implementation process documentation, and VERILOG HDL code, hoping to help people in need, thank you Platform: |
Size: 2071552 |
Author:shenshunxiao |
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Description: FPGA实现uart的通信，用verilog语言编写，UART是常用的通信方式，值得学习-The FPGA implementation of uart communication, written in verilog language, uart is a common way of communication, worth learning Platform: |
Size: 6068224 |
Author:罗强 |
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