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[SourceCode] DCT实现Verilog HDL的数字图像处理源代码

Description: DCT实现Verilog HDL的数字图像处理
Platform: | Size: 31657 | Author: juyong | Hits:

[VHDL-FPGA-Verilog] ad_DCT

Description: verilog 编程 有测试文档 基于查表结构实现 离散余弦变换dct 来源：opencores -Verilog Programming is based on the test documents Lookup structure for a discrete cosine transform Extra Source : opencores
Platform: | Size: 33792 | Author: 周信均 | Hits:

[Compress-Decompress algrithms] jpeg_encoder

Description: 完整的jpeg encoder verilog code,DCT部分採用1991 IEEE transection paper,利用skew circular convolution來實現精簡電路-complete jpeg encoder Verilog code, DCT is partly based on the IEEE 1991 transection paper, using skew circular convolutions to achieve streamlining circuit
Platform: | Size: 25600 | Author: 李寧 | Hits:

[Windows Develop] dct_mac

Description: dct verilog code for image -Extra Verilog code for image
Platform: | Size: 2048 | Author: zhang chi | Hits:

[Compress-Decompress algrithms] 601792346200732319490634862

Description: jpeg压缩中的DCT蝶型算法verilog代码-jpeg DCT compression algorithm verilog code BUTTERFLY
Platform: | Size: 5120 | Author: wuguanying | Hits:

[Special Effects] DCTofJPEG

Description: 用verilog代码写的JPEG压缩核心模块DCT变换之蝶形单元算法-verilog code written using JPEG compression core module DCT's butterfly modules algorithm
Platform: | Size: 1024 | Author: 叶人杰 | Hits:

[Graph program] DCT-vhdl

Description: 这是一个二维 8*8块的离散余弦变换(DCT)以及反变换(IDCT)算法,采用VHDL实现-This is a two-dimensional 8* 8 discrete cosine transform (DCT) and inverse transform (IDCT) algorithms using VHDL realize
Platform: | Size: 10240 | Author: liujl | Hits:

[VHDL-FPGA-Verilog] dct

Description: 里面含有vhdl和verilog 版本,很好用!dct变换用得很多啊!-Which contains a VHDL and Verilog versions of very good use! Dct transform with a lot ah!
Platform: | Size: 124928 | Author: 萧勇 | Hits:

[2D Graphic] dct

Description: DCT的Verilog 程序，用QUARTUS进行开发-DCT-Verilog procedures developed by Quartus
Platform: | Size: 3124224 | Author: 张伟 | Hits:

[VHDL-FPGA-Verilog] DCT

Description: 用verilog语言实现DCT编解码 附有DCT的说明-Using Verilog language realize DCT codec with a description of DCT
Platform: | Size: 65536 | Author: 周韧研 | Hits:

[VHDL-FPGA-Verilog] dct

Description: 离散余弦变换的verilog源代码，经过验证可实现-Discrete cosine transform of Verilog source code can be verified
Platform: | Size: 27648 | Author: 罗伟 | Hits:

[VHDL-FPGA-Verilog] Dct_verilog

Description: 采用verilog hdl 语言实现整形dct算法，设计合理，算法简单，是红色逻辑开发板试验程序，值得一看。-Verilog hdl language used plastic realize DCT algorithm, rational design algorithm is simple and logical development board is red test procedures, worth a visit.
Platform: | Size: 4096 | Author: panyouyu | Hits:

[OpenGL program] DCT

Description: 用Verilog HDL编写的离散余弦变换，可用于视频图像压缩，并在modelsim SE6.0中仿真通过-Verilog HDL prepared with discrete cosine transform can be used for video image compression, and modelsim SE6.0 simulation through
Platform: | Size: 1024 | Author: yangyanwen | Hits:

[VHDL-FPGA-Verilog] DCT+

Description: 改进的DCT算法设计，veriloghdl实现-Improved DCT algorithm design, veriloghdl realize
Platform: | Size: 313344 | Author: lyc84122 | Hits:

[VHDL-FPGA-Verilog] DCT

Description: altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序，已经过matlab 和modelsim 验证，文件中包含TESTBENCH ，直接可用-altera fpga verilog design table DCT-based search procedures and zigzag scanning procedures, and ModelSim matlab has been verified, the document contains TESTBENCH, directly available
Platform: | Size: 15400960 | Author: alison | Hits:

[Special Effects] butterfly-verilog

Description: VHDL的DCT变换.蝶型算法,很好用的,希望能有帮助-The DCT transform VHDL. Butterfly algorithm, very good with the hope that it can be helpful
Platform: | Size: 1024 | Author: zhaoyizhi | Hits:

[Compress-Decompress algrithms] verilog_dct_serial

Description: Verilog dct + description]-Verilog dct+ description]
Platform: | Size: 24576 | Author: asia | Hits:

[Embeded-SCM Develop] dct

Description: DCT的FPGA实现，用verilog语言把DCT的快速算法即LOEFFLER算法表示出来。-DCT-FPGA, with the verilog language to the fast DCT algorithm, which is LOEFFLER algorithm that out.
Platform: | Size: 105472 | Author: 蓝冰 | Hits:

[VHDL-FPGA-Verilog] dct

Description: all ok...4 Dec 2009 ... In this method the 2-Dimensional DCT is obtained by taking two ... column-wise 1D DCT is ascertained which gives the 2D DCT of the data. ... The design is done in Verilog HDL and the simulation is done in Modelsim 6.3b.
Platform: | Size: 1024 | Author: haziq36 | Hits:

[VHDL-FPGA-Verilog] verilog dct

Description: 其使用模块的代码风格来编写，能够8点dct的转换(Its use of the module's code style to write, to 8 dct conversion)
Platform: | Size: 34816 | Author: 未曾走远 | Hits:
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