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Description: 实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波
A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成
各种波形的线形叠加输出。
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Size: 9404 |
Author: zhanyi |
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Description: 设计一个VGA图像显示控制器，使其实现以下功能----
1． 显示模式为640╳480╳60Hz。
2． 用拨码开关控制R，G，B（每个2位），使显示器可以显示64种纯色。
3． 在显示器上显示横向彩条信号（至少六种颜色）。
4． 在显示器上显示纵向彩条信号（至少八种颜色）。
5． 在显示器上显示自行设定的图形，图像等。
6． 选做，自拟其他功能。
所利用到的元器件有：
电脑，显示器，vga接口转换模块，
数字电子电路实验开发板，30Mhz晶振，下载线，电源等
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Size: 837193 |
Author: wangguangchao008@163.com |
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Description: SystemC片上系统设计的源代码：
书籍介绍：
SystemC是被实践证明的优秀的系统设计描述语言，它能够完成从系统到门级、从软件到硬件、从设计到验证的全部描述。SystemC 2.01已作为一个稳定的版本提交到IEEE，申请国际标准。
本书为配合清华大学电子工程系SystemC相关课程的教学而编写。全书分9章，内容包括：硬件描述语言的发展史；SystemC出现的历史背景和片上系统设计方法学概述；SystemC的基本语法；SystemC的寄存器传输级设计和SystemC的可综合语言子集，以及根据作者设计经历归结的RTL设计准则和经验；接口、端口和通道等SystemC行为建模实例——片上总线系统；SystemC与VHDL/Verilog HDL的比较；SystemC的验证标准和验证方法学；SystemC开发工具SystemC_win、WaveViewer等，以及使用MATLAB进行SystemC算法模块的验证。每一章都精心编写了课后习题以配合教学的需要。
本书可作为大学电子设计自动化（EDA）相关课程教材，也可供电子工程技术人员作为SystemC设计、应用开发的技术参考书。本书丰富的实例源代码特别适合初学者根据内容实际运行、体会，举一反三，以掌握SystemC进行应用系统设计。 -SystemC system on chip design source : books introduced : SystemC has been proven in practice is an excellent system design description language, it can be completed from the system level to the door, from hardware to software, from design to verification of all description. SystemC has 2.01 as a stable version submitted to the IEEE, the application of international standards. The book to tie in electronic engineering at Tsinghua University SystemC related courses and preparation of teaching. Book nine chapters, including : hardware description language development history; SystemC is the historical background and system-on-chip design methodology outlined; SystemC basic grammar; SystemC register-transfer-level design and synthesis of SystemC language subset, as well as design experience b
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Size: 2640896 |
Author: c.li |
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Description: VHDL 8位无符号除法器 试验报告
计算前在A和B端口输入被除数和除数，然后在Load线上送高电平，把数据存到除法计算电路内部，然后经过若干个时钟周期，计算出商和余数，并在C和D端输出。
其实现方法是，将除法器分为两个状态：等待状态与运算状态。
开始时除法器处于等待状态，在该状态，在每一时钟上升沿，采样Load信号线，若是低电平，则仍处于等待状态，如果采样到高电平，除法器读取A，B数据线上的输入数据，保存到内部寄存器a_r，b_r，置c_r为0，d_r为a_r，判断除数是否为零，若不为零则进入运算状态。
-VHDL eight unsigned divider calculation of the test report before the A and B ports to import and dividend divider, and then sent to I Load line, the data are uploaded to the internal division calculation circuit, and then after a number of clock cycles, and worked out more than a few, and in the C-and D output. Their method is to be divided into two division for the state : waiting for the state and Operational state. At the beginning divider waiting for the state, in the state in each clock rising edge, sampling Load signal line, if low-level, it is still waiting for the state, if the sampling to allow high output, Divider read A, B online data input data, preservation of the internal registers renovation r, b_r, home c_r 0, d_r a_r to determine whether the divisor zero, if not zero, it
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Author: aa |
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Description: fpdiv_vhdl四位除法器
-- DESCRIPTION : Signed divider
-- A (A) input width : 4
-- B (B) input width : 4
-- Q (data_out) output width : 4
-- DIV_BY_0 (DIVz) output active : high-fpdiv_vhdl four divider-- DESCRIPTION : Signed divider-- A (A) input width : 4-- B (B) input width : 4-- Q (data_out) output width : 4-- DIV_BY_0 (DIVz) output active : high
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Size: 1024 |
Author: 张洪 |
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Description: vhdl波形发生程序.实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波
A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成
各种波形的线形叠加输出。
-vhdl waveform occurred procedures. 4 achieve common sinusoidal waveform, 1.30, sawtooth, square-wave (A, B) the frequency and amplitude control output (square A duty cycle is also controllable), can store data of arbitrary waveform characteristics and able to reproduce the waveform, but also through a variety of linear superposition of the waveform output.
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Size: 10240 |
Author: 江汉 |
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Description: Verilog HDL: Magnitude
For a vector (a,b), the magnitude representation is the following:
A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm.
-Verilog HDL : For a vector magnitude (a, b), the magnitude representation is the following : A common approach to implementing thes e arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonome tric functions of sine, cosine, magn itude, and phase using an iterative process. It i 's made up of a series of micro-rotations of the v ector by a set of predetermined cons tants, which are powers of two. Using binary ar praxiology metic, this algorithm essentially replaces m ultipliers with shift and add operations. In a Stratix
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Size: 12288 |
Author: 郝晋 |
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Description: 利用最新的嵌入式开发工具EDK，在FPGA 中完成对PDIUSBD12 的硬件定制和固件编程，从而在FPGA
中实现U S B 控制器， 并最终完成U S B 的枚举过程、驱动程序的开发和简单的应用。-Using the latest embedded development tools, EDK, in the FPGA completes its PDIUSBD12 custom hardware and firmware programming, in order to realize USB controller in the FPGA, and ultimately complete the USB enumeration process of driver development and simple应用.
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Size: 50176 |
Author: pengrong |
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Description: vhdl mfsk
多进制数字频率调制(MFSK)也称多元调频或多频制。MFSK系统是 2FSK(二频键控)系统的推广，该系统有 M个 不同的载波频率可供选择．每一个载波频率对应一个 M进制码 元信息，即用多个频率不同的正弦波分别代表不同的数字信号，在某一码元时间内只发送其中一个频率。-vhdl mfsk M-ary digital frequency modulation (MFSK), also known as multi-frequency or multi-frequency system. MFSK system is 2FSK (b Frequency Shift Keying) system, the promotion, the system has M different carrier frequencies to choose from. Each carrier frequency corresponds to an M-band meta-information code, which uses a number of different sine wave frequency, respectively, representing different digital signal, in a symbol time to send only one frequency.
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Size: 1024 |
Author: mzizai |
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Description: 利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试方便、故障率低、修改升级容易等特点。
本设计采用自顶向下、混合输入方式（原理图输入—顶层文件连接和VHDL语言输入—各模块程序设计）实现数字钟的设计、下载和调试。
一、 功能说明
已完成功能
1. 完成秒／分／时的依次显示并正确计数；
2. 秒／分／时各段个位满10正确进位，秒／分能做到满60向前进位；
3. 定时闹钟：实现整点报时，又扬声器发出报时声音；
4. 时间设置，也就是手动调时功能：当认为时钟不准确时，可以分别对分／时钟进行调整；
5. 利用多余两位数码管完成秒表显示：A、精度达10ms；B、可以清零；C、完成暂停
可以随时记时、暂停后记录数据。
待改进功能：
1. 闹钟只是整点报时，不能手动设置报时时间，遗憾之一；
2. 秒表不能向秒进位，也就是最多只能记时100ms；
3. 秒表暂停记录数据后不能在原有基础上继续计时，而是复位重新开始。
【注意】秒表为后来添加功能，所以有很多功能不成熟！
-err
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Size: 677888 |
Author: luoliang |
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Description: 罗马尼亚克鲁日工程大学Mircea Dă bâ can, PhD提供的示波器开发全文挡及C,VHDL代码.-Romania cluj Engineering University Mircea D
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Size: 975872 |
Author: hxf |
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Description: 设计一个由甲、乙双方参赛，有裁判的3人乒乓球游戏机-Design of an A, B or both sides participating, there are 3 referee s table tennis game
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Size: 2048 |
Author: 李萧 |
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Description: 除法器的设计本文所采用的除法原理是：对于八位无符号被除数A，先对A转换成高八位是0低八位是A的数C，在时钟脉冲的每个上升沿C 向左移动一位，最后一位补零，同时判断C的高八位是否大于除数B，如是则C的高八位减去B，同时进行移位操作，将C的第二位置1。否则，继续移位操作。经过八个周期后，所得到的C的高八位为余数，第八位为商。从图(1)可清楚地看出此除法器的工作原理。此除法器主要包括比较器、减法器、移位器、控制器等模块。-Divider design used in this paper, the principle of division is: For the eight unsigned dividend A, the first of A into the high-low 8 0 8 is the A number of C, in each clock rising edge to the left C Mobile One, and finally a zero, at the same time to determine whether C is greater than the high-8 divisor B, so is the high C 8 minus B, at the same time shift operation, the location will be C s second one. Otherwise, continue to shift operation. After eight cycles, received a high C for more than eight the number of eighth place for the business. From Figure (1) can clearly see that the divider works. This mainly includes divider comparators, subtraction, and shifter, controller modules.
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Size: 1024 |
Author: lyy |
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Description: 本程序实现了一个序列检测器。当一串待检测的串行数据进入检测器后，若此数在每一位的连续检测中都与预置的密码数相同，则输出“A”,否则仍然输出“B”。-This procedure implements a sequence detector. When a string of serial data to be tested after entering the detector, if the number in each successive detection with the same number of preset password, then output A , otherwise the output is still B .
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Size: 1024 |
Author: liushenshen |
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Description: 一个QEP电路的verilog代码。输入信号是光电编码器的A相和B相信号和一个处理时钟，输出的是计数信号和方向信号。-A QEP circuit Verilog code. Input signal is the optical encoder of the A phase and B and believe that a deal with the clock, the output is the count signal and direction signal.
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Size: 1024 |
Author: 张洁 |
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Description: HDB3码的VHDL实现
共三个模块：插入V、插入B以及单双极性变换-VHDL code HDB3 realize a total of three modules: Insert V, insert B, as well as single-and double-polar transform
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Size: 1024 |
Author: Xingzhi |
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Description: 实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波
A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成
各种波形的线形叠加输出。
-Realize four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency, magnitude controllable output (square wave A, is also a controllable duty cycle), can store arbitrary waveform feature data and can reproduce the waveform, but also completed a variety of linear superposition of the output waveform.
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Size: 9216 |
Author: zhanyi |
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Description: vhdl编写的将二进制转BCD码的程序.直接源代码，适合新手编程，语法学习-BCD
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Size: 202752 |
Author: yjh |
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Description: 用VHDL语言描述和实现乘法累加器设计,4位的被乘数X和4位的乘数Y输入后，暂存在寄存器4位的寄存器A和B中，寄存器A和B的输出首先相乘，得到8位乘积，该乘积再与8位寄存器C的输出相加，相加结果保存在寄存器C中。寄存器C的输出也是系统输出Z。(原创，里面有乘法部分和累加部分可以单独提出来，很好用)
-With the VHDL language to describe the design and realization of multiplier-accumulator, four of multiplicand X and 4-bit multiplier Y input, the temporary 4-bit registers in the register A and B, registers A and B multiplied by the output of the first, to be 8-bit product, the product further with the 8-bit output of register C, the sum of, the sum of the results stored in register C,. The output register C is also the system output Z. (Original, which are multiply and accumulate some part may be raised separately, very good use)
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Author: jlz |
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Description: 高楼电梯自动控制系统(Windows平台上运行的ispLEVER编程软件。
):
1统控制的电梯往返于1-9层楼。
2客要去的楼层数可手动输入并显示（设为A数）。
3梯运行的楼层数可自动显示（设为B数）。
4A>B时，系统能输出使三相电机正转的时序信号，使电梯上升；
当A<B时，系统能输出使三相电机反转的时序信号，使电梯下降；
当A=B时，系统能输出使三相电机停机的信号，使电梯停止运行并开门；
5是上升还是下降各层电梯门外应有指示，各层电梯门外应有使电梯上升或下降到乘客所在楼层的控制开关。
注：此为word文档，但里面有源代码。-High-rise elevator control system (Windows platform programming software running on the ispLEVER.
):
An elevator control system and from 1-9 floors.
2, the number of passengers going to the floor can manually enter and display (Make A number).
3 ladder run automatically display the number of floors (Set B number).
4A> B, the system can output three-phase motor is transferred to the timing signal to lift up
When A <B, the system can output three-phase motor to reverse the timing signal to the lift down
When A = B, the system can output a signal to shut down three-phase motor, so that the lift stops and open the door
5 is increasing or decreasing the lift on each floor outside the door should be directed, due to lift on each floor outside the elevator up or down to the floor where the passenger control switch.
Note: This is a word document, but inside the source code.
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