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[VHDL-FPGA-Verilog] ref-ddr-sdram-vhdl DL : 0: 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
Update : 2025-02-17 Size : 1007kb Publisher : 包盛花
[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl DL : 0: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Update : 2025-02-17 Size : 758kb Publisher : 张涛
[VHDL-FPGA-Verilog] ddr DL : 0: 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
Update : 2025-02-17 Size : 2kb Publisher : 孙强
[VHDL-FPGA-Verilog] ddr_sdram_controller_vhdl DL : 0: ddr_sdram控制器的vhdl代码,里面的地址和数据长度可配置,能满足不同用户的需要.-ddr_sdram controller vhdl code, which addresses and the data length can be configured, meet the needs of different users.
Update : 2025-02-17 Size : 13kb Publisher : hxwf801
[Other] ref-ddr-sdram-vhdl DL : 0: 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
Update : 2025-02-17 Size : 427kb Publisher : kevin
[Documents] SDRAM-VHDL DL : 0: SDRAM控制器的VHDL实现，pdf格式，有需要多的，联系我-SDRAM controller VHDL, pdf format, it needs more, Contact
Update : 2025-02-17 Size : 122kb Publisher :
[VHDL-FPGA-Verilog] cpu-leon3-altera-ep2s60-ddr DL : 0: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的DDR控制器程序！-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of DDR controller program!
Update : 2025-02-17 Size : 735kb Publisher : zhao onely
[VHDL-FPGA-Verilog] DDR2_module_VHDL_test(Rev0.1) DL : 0: ddr 2 接口读写测试模块 ddr 2 接口读写测试模块 -ddr 2 interface test module ddr 2 read and write interface to read and write test module
Update : 2025-02-17 Size : 123kb Publisher : 骑士
[VHDL-FPGA-Verilog] t26a_ibis DL : 0: ddr sdram 的控制代码，采用VHDL语言书写-ddr sdram control code, the use of VHDL language
Update : 2025-02-17 Size : 275kb Publisher : zxb
[Other] ddr_ctrlv DL : 0: ddr ram controller vhdl code
Update : 2025-02-17 Size : 54kb Publisher : heyong
[Windows Develop] ddr_sdr_V1_0 DL : 0: 关于DDR控制器方面的，可以看看，里面有较完整的代码和说明。-On the DDR controllers, you can see, there are more complete code and description.
Update : 2025-02-17 Size : 38kb Publisher : yuhl
[VHDL-FPGA-Verilog] rtl DL : 0: DDR控制器已通过FPGA 验证大家不要错过哦-DDR controller has passed FPGA to verify that we will not miss Oh
Update : 2025-02-17 Size : 51kb Publisher : kin
[Other] 128Mb_ddr DL : 0: 128Mb DDR verilog源程序-128Mb DDR verilog source code
Update : 2025-02-17 Size : 23kb Publisher : tiantian
[VHDL-FPGA-Verilog] DDR_SDRAM_verilog DL : 0: DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的-DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good
Update : 2025-02-17 Size : 735kb Publisher : 宋珂
[VHDL-FPGA-Verilog] DDR_SDRAM_controller DL : 0: ddr sdram 的vhdl实现，包括各个模块的实现以及仿真文件-ddr sdram realization of VHDL, including the realization of each module as well as the simulation file
Update : 2025-02-17 Size : 998kb Publisher : shroy
[VHDL-FPGA-Verilog] DDR_SDRAM_controller DL : 0: DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.-DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O
Update : 2025-02-17 Size : 129kb Publisher : xbl
[VHDL-FPGA-Verilog] ref-ddr-sdram-vhdl DL : 0: 基于VHDL编写的DDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the DDR-SDRAM controller programming, is currently the industry s commonly used RAM controller
Update : 2025-02-17 Size : 1007kb Publisher : wfs
[Software Engineering] 20060510191318991 DL : 0: ALTERA公司DDR ram controller资料-ALTERA company DDR ram controller information
Update : 2025-02-17 Size : 2.15mb Publisher : 盛雪飞
[VHDL-FPGA-Verilog] ddr-sdram--chengxu DL : 0: ddr的控制程序，实用Verilog语言实现的非常的具体，非常无奈过的实用。-ddr
Update : 2025-02-17 Size : 14kb Publisher : 张杰
[VHDL-FPGA-Verilog] ddr-sdram DL : 0: DDR SDRAM控制器verilog代码及中文说明文档,对DDR开发很有用的哈。-Verilog source code for DDR SDRAM controler design,including guide book in chinese.
Update : 2025-02-17 Size : 902kb Publisher : runxin

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