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[VHDL-FPGA-Verilog] 20051113104111170

Description: FPGA的VHDL设计经验总结《小型微型计算机系统》2003年7月-FPGA VHDL design experience, "small micro-computer system," July 2003
Platform: | Size: 198656 | Author: 天天 | Hits:

[Other] 8051_ip_core

Description: 8051微控制器的ip 核的vhdl源代码,其中包含了相应的测试程序.-8051 micro-controller ip nuclear vhdl source code, which contains the corresponding test procedures.
Platform: | Size: 339968 | Author: 大为 | Hits:

[VHDL-FPGA-Verilog] magnitude

Description: Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm. -Verilog HDL : For a vector magnitude (a, b), the magnitude representation is the following : A common approach to implementing thes e arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonome tric functions of sine, cosine, magn itude, and phase using an iterative process. It i 's made up of a series of micro-rotations of the v ector by a set of predetermined cons tants, which are powers of two. Using binary ar praxiology metic, this algorithm essentially replaces m ultipliers with shift and add operations. In a Stratix
Platform: | Size: 12288 | Author: 郝晋 | Hits:

[Crack Hack] micro-UARTsource_V

Description: UART(即Universal Asynchronous Receiver Transmitter 通用异步收发器)是广泛使用的串行数据传输协议。UART允许在串行链路上进行全双工的通信。-UART (ie Universal Asynchronous Receiver Transmitter Universal Asynchronous Receiver Transmitter) is a widely used serial data transfer protocol. UART allows for full-duplex serial link communications.
Platform: | Size: 5120 | Author: 陈 | Hits:

[VHDL-FPGA-Verilog] computer5

Description: 一种RISC结构8位微控制器的设计与实现-The structure of a RISC micro-controller' s 8 Design and Implementation
Platform: | Size: 8429568 | Author: steven | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 用VHDL语言设计简单的CPU，重点设计微操作代码，然后设计CPU各组成模块，最后根据设计的微操作设计微指令，验证设计的正确性。可基本实现加、减、乘、除、移位、循环等操作。-VHDL language is designed to be simple to use the CPU, the focus of the design of micro-operation code, and then design the components of CPU module designed the final design of the micro-operation microinstruction to verify the correctness of the design. Can achieve the basic add, subtract, multiply, divide, transfer, recycling and other operations.
Platform: | Size: 1268736 | Author: Rachel | Hits:

[SCM] shukongzhiliudianyuan

Description: 介绍了一种闭环智能数控直流电流源的设计原理和实施方案，该方案采用自行设计制作的高精度电压源，利用单片机、PWM和运算放大器构成A/DD/A转换器来控制场效应管导通状态的原理，达到了输出恒流的目的。整个系统采用89C58单片机作为主控部件，将预置电流值数据送入D/A转换器，经硬件电路变换为恒定的直流输出，同时使用采样电阻将实际输出电流转换成电压送入A/D转换器，并将其反馈到单片机中构成闭环系统，进而实现预设值和实际值的比较，再通过调整D /A转换器输出的电压来改变场效应管的导通状态，减小了实际值与预设值之间的误差，实现了电流可预置、可步进调整、输出的电流信号可直接数字显示的功能。采用硬件闭环、软件闭环、软件实时积分、实时滤波的方法，锁定输出电流，从而实现了高精度恒流源的目的。此次所设计的电流源具有精度高、结构简单、工作稳定、操作方便、成本低廉、带负载能力强等优点-The scheme adapts high precision voltage source designed by ourselves Micro Control Unit (MCU) D/A converter and amplifier to control the transmitting state of field effect transistor which attains constant current. The system adapts MCU 89c52 as main control part the output current is transformed into the voltage by sample resistant and the voltage is sent to D/A converter and then sent to the MCU compared with the setting current. If there exist errors we should adapt D/A converter output and change the transmitting state of field effect transistor. The actual value is directed to the setting value. The direct current reaches the constant value. The closed loop control and PID arithmetic is used to realize high precision and wide range in the software design part. The intelligent current source realizes that the output current can be preset adjusted step by step and displayed in digit directly. Above functions are operated by keyboard within the current source. The stability of this
Platform: | Size: 2048 | Author: zhendongzhao | Hits:

[VHDL-FPGA-Verilog] logic_app

Description: 中际赛微15期培训班 逻辑功能试验 2009-5-Competition in 15 micro-logic function tests training 2009-5
Platform: | Size: 1212416 | Author: xinzhi | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: A vhdl implementation of 8051 micro controller. this code is from oregano.
Platform: | Size: 100352 | Author: baba | Hits:

[Technology Management] dds9851

Description: 本文主要介绍的是采用直接数字频率合成的短波信号发生器，它主要以微电脑控制部分、直接数字频率合成（DDS）部分、数字锁相环频率合成部分、背光液晶显示部分、功率放大部分等组成。该软件系统采用菜单形式进行操作，操作方便明了，增加了很多功能。它通过启动DDS后，把内存缓存区的数据送到DDS后输出相应的频率，并把数据转换为BCD码，送到液晶显示器进行显示。该系统输出稳定度、精度极高，适用于当代的尖端的通信系统和精密的高精度仪器。-This paper describes the use of direct digital frequency synthesis of short-wave signal generator, which is part of a micro-computer control, Direct Digital Synthesis (DDS) of the digital part of PLL frequency synthesizer, backlit liquid crystal display of the power amplifier, etc. composition. The menu system uses the form of software to operate, easy to operate and clear, increase in the number of features. DDS through start after the memory cache after the data to the DDS output corresponding frequency, and the data is converted to BCD code to the LCD display. The output of the system stability, high precision for cutting-edge contemporary and sophisticated communication systems high-precision instruments
Platform: | Size: 466944 | Author: xiang | Hits:

[VHDL-FPGA-Verilog] micro

Description: 16 cpu design VHDL source code, including alu, clock, memory and other parts of the design
Platform: | Size: 30720 | Author: mojo | Hits:

[VHDL-FPGA-Verilog] pico_code

Description: pico blaze VHDL code for write to micro SD flash with spi protocol
Platform: | Size: 19456 | Author: ali | Hits:

[VHDL-FPGA-Verilog] Microprogramcontroller

Description: 微程序控制器部件实验，使用VHDL语言使用Quartus测试通过，模拟CPU-Micro-program controller component experiments, the use of VHDL language use Quartus test, simulation CPU
Platform: | Size: 752640 | Author: 糖糖 | Hits:

[Embeded-SCM Develop] Micro-program

Description: 微程序控制电路是CPU 控制器的核心电路，控制产生指令执行时各部件协调工作所需的所有控制信号，以及下一条指令的地址。微程序控制器的组成如图6-12 所示，主要由三个部分组成，分别是微指令控制电路、微地址寄存器和微指令存储器lpm_rom 其中微指令控制电路用组合电路对指令中的1[7..2] 、操作台控制信号SWA 和SWB 的状态、状态寄存器的输出状态FC 、FZ ，产生微地址变化的控制信号，实现对微地址控制:微地址寄存器控制电路的基本输入信号是微指令存储器的下地址字段M[6..1] ，同时还受微指令控制电路的输出信号SE[6..1]和复位信号RST 的控制，输出下一个微指令的地址:控制存储器由FPGA 中的LPM ROM 构成，输出24 位控制信号。在24 位控制信号中，微命令信号为18 位，微地址信号豆位。在口时刻将打入微地址寄存器UA 的内容，即为下一条微指令地址.当T4时刻进行测试判别时，转移逻辑满足条件后输出的负脉冲，通过强制端将某一触发器置为"1"状态，完成地址修改。微程序控制器中的微控制代码可以通过对FPGA 中LPMß OM 的配置进行输入，通过编辑LPM ROM.mif 文件来修改微控制代码。详细情况可参考LPIÞ CROM的配置方法。微指令控制电路内部结构如图6-2 ， 6-3. 6-13 所示-Micro-program control circuit is the core CPU controller circuit, the control instruction execution produces the coordination of all parts of all the necessary control signals, and the next instruction address. The composition of micro-program controller shown in Figure 6-12, the main three components, namely, microinstruction control circuit, micro-address register and the microcode memory lpm_rom microcode control circuit which combination circuit with instruction in the 1 [ 7 .. 2], SWA and SWB console control signal state, the state register output state FC, FZ, produce changes in micro-address control signals, to realize the micro-address control: micro-address register control circuit input signal is the basic micro- The next address field instruction memory M [6 .. 1], but also by the microcode control circuit output signal SE [6 .. 1] and reset control signal RST, the output of the next microinstruction address: control memory by the FPGA in the LPM ROM form, the output 24-bit
Platform: | Size: 2584576 | Author: 623902748 | Hits:

[VHDL-FPGA-Verilog] can_latest[1].tar

Description: CAN，全称“Controller Area Network”，即控制器局域网，是国际上应用最广泛的现场总线之一。最初，CAN被设计作为汽车环境中的微控制器通讯，在车载各电子控制装置ECU之间交换信息，形成汽车电子控制网络。比如：发动机管理系统、变速箱控制器、仪表装备、电子主干系统中，均嵌入CAN控制装置。 -CAN, full name of the " Controller Area Network" , the Controller Area Network, is internationally the most widely used field bus. Initially, CAN is designed as a vehicle environment, the micro-controller communications, in-vehicle electronic control unit ECU of the exchange of information between the formation of automotive electronic control network. For example: engine management systems, transmission controllers, instrumentation and equipment, electronic backbone of the system are embedded CAN control.
Platform: | Size: 1149952 | Author: zhaohaiting | Hits:

[VHDL-FPGA-Verilog] Micro_uart

Description: Micro-uart source code
Platform: | Size: 1465344 | Author: Huang | Hits:

[VHDL-FPGA-Verilog] The--VHDL-code-of-I2C

Description: 该程序采用延时接收比较来实现仲裁的方法，使不具有I2C接口的普通微控制器（MCU）能够实现模拟I2C总线的多主通信。-This program is to realize the delay receiving the arbitration method, do not have the I2C interface of ordinary micro controller (MCU) can simulate the I2C bus more than the main communication.
Platform: | Size: 4096 | Author: 西土瓦 | Hits:

[VHDL-FPGA-Verilog] micro-processor

Description: 这是一个8位微处理器的vhdl设计代码。-This is the design of a 8-bit micro-processor.
Platform: | Size: 4096 | Author: baoshu | Hits:

[VHDL-FPGA-Verilog] Micro

Description: build micro with verilog/vhdl
Platform: | Size: 904192 | Author: Hamid | Hits:

[VHDL-FPGA-Verilog] ccsuemupc条件跳转(1)

Description: 设计一个模型机，具体设计要求如下： （1）设计指令系统，要求有取数指令、加法指令、跳转指令、停机指令等 （2）设计指令格式、微指令格式 、微程序 、时序电路 、数据通路，完成cpu的设计。 （3）利用模块化设计，分别设计存储器模块、运算器模块、时序电路模块、微程序控制器模块、显示模块等，最后进行系统的顶层设计，完成复杂模型机的设计与实现测试 （4）根据任务，完成主程序的设计，同时把主程序翻译成目标代码，写入主存，仿真下载测试。(Design a model machine, the specific design requirements are as follows: (1) design instruction system, required to have number instructions, addition instructions, jump instructions, downtime instructions and so on (2) Design instruction format, micro-instruction format, micro-program, time series circuit, data path, complete the design of the CPU. (3) The use of modular design, respectively design memory module, operator module, time series circuit module, microcontroller Controller module, display module, etc., and finally carry out the top layer design of the system, complete the design and implementation of complex model machine test (4) According to the task, complete the design of the main program, while translating the main program into the target code, Write the deposit, simulation download test.)
Platform: | Size: 1189888 | Author: 12332122 | Hits:
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