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[Other resource] ref-sdr-sdram-vhdl

Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Platform: | Size: 776642 | Author: 张涛 | Hits:

[Other resource] sdr sdram controller

Description: ALTERA sdram vhdl与verilog参考设计-Altera SDRAM VHDL and Verilog reference design
Platform: | Size: 2459435 | Author: 陈东平 | Hits:

[Other] ref-sdr-sdram-vhdl

Description: FPGA连接SDRAM的源程序，VHDL语言实现，功能基本完全。应用效果好。
Platform: | Size: 731727 | Author: young | Hits:

[Other resource] ref-sdr-sdram-vhdl

Description: 标准SDR SDRAM控制器参考设计_verilog_lattice\\sdr_ctrl.v
Platform: | Size: 776642 | Author: 王廷龙 | Hits:

[SourceCode] SDR-SDRAM-vhdl

Description: SDR-SDRAM-vhdl单个SDRAM的控制，通过它可以学习了解SDRAM的时序等，很有帮助哦 ！
Platform: | Size: 717771 | Author: zsy5460 | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl

Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Platform: | Size: 776192 | Author: 张涛 | Hits:

[VHDL-FPGA-Verilog] sdr sdram controller

Description: ALTERA sdram vhdl与verilog参考设计-Altera SDRAM VHDL and Verilog reference design
Platform: | Size: 2458624 | Author: 陈东平 | Hits:

[Other] ref-sdr-sdram-vhdl

Description: FPGA连接SDRAM的源程序，VHDL语言实现，功能基本完全。应用效果好。-FPGA connected SDRAM source, VHDL language, the basic function fully. Application effective.
Platform: | Size: 732160 | Author: young | Hits:

[Other] ref-sdr-sdram-verilog

Description: sdram控制器的开发程序，还有文档，可以参考以下-SDRAM controller development process, there is a document, you can refer to the following
Platform: | Size: 776192 | Author: 王鹏 | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl

Description: 标准SDR SDRAM控制器参考设计_verilog_lattice\sdr_ctrl.v-Standard SDR SDRAM Controller Reference Design _verilog_latticesdr_ctrl.v
Platform: | Size: 776192 | Author: 王廷龙 | Hits:

[VHDL-FPGA-Verilog] 61EDA_C52

Description: 标准SDR SDRAM控制器参考设计，有助于大家学习和参考-Standard SDR SDRAM controller reference design will help everyone to learn and reference
Platform: | Size: 205824 | Author: 王廷龙 | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-verilog

Description: SDRAM的vegilog代码，做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM
Platform: | Size: 717824 | Author: 吴厚航 | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-verilog

Description: 标准SRD SDRAM控制器参考设计，altera提供 Verilog代码,带有使用手册，大家试试交流一下 -Standard SRD SDRAM controller reference design, altera provide Verilog code, with user manual, we try to exchange some
Platform: | Size: 776192 | Author: 费尔德 | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl

Description: 基于VHDL编写的SDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the SDR-SDRAM controller programming, is now commonly used in industry RAM controller
Platform: | Size: 1013760 | Author: wfs | Hits:

[VHDL-FPGA-Verilog] SDR_SDRAM_vhd

Description: SDR SDRAM的VHDL描述，比较详细，还有数据手册-SDR SDRAM the VHDL description, more detailed, have data sheet
Platform: | Size: 717824 | Author: 顾康 | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: verilog 128位 突发4. sdr fpga控制器-verilog 128 bit unexpected 4. sdr fpga controller
Platform: | Size: 119808 | Author: pudnrtest | Hits:

[VHDL-FPGA-Verilog] WRCTRL

Description: this VHDL Program get a 64 bit data and send it to a SDRAM-controller block to write into SDRAM and then get a 64bits data from SDR-block
Platform: | Size: 2048 | Author: Taher Aghazadeh | Hits:

[VHDL-FPGA-Verilog] xapp856

Description: 基于FPGA的SFI接口实现（VHDL，Verilog and doc）-SFI-4.1 16-Channel SDR Interface with Bus Alignment
Platform: | Size: 556032 | Author: wicky | Hits:

[VHDL-FPGA-Verilog] xapp622

Description: 644 MHz SDR LVDS 发射器/接收器(verilog and doc)-644-MHz SDR LVDS Transmitter/Receiver
Platform: | Size: 355328 | Author: wicky | Hits:

[Other] SDR-SDRAM-ctl1

Description: SDR SDRAM控制器，FPGA vhdl代码-SDR SDRAM Controller
Platform: | Size: 718848 | Author: | Hits:
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