Search - VHDL TV

[VHDL-FPGA-Verilog] 9.16fifoasi

Description: 主要完成数字电视前端信号处理和缓冲作用的verilog源代码，可以直接使用 -the major digital TV front-end signal processing and buffer the Verilog source code can be used directly
Platform: | Size: 2761728 | Author: yjb_21cn | Hits:

[matlab] ldpcdecoderandencoder

Description: 这是国标数字电视地面传输标准里信道编解码器的MATLAB程序，用的是LLR-BP的解码算法，请大家指正。另有根据国标生成的生成矩阵和校验矩阵稍后传上来-This is the national standard of digital TV terrestrial transmission standard in channel codec MATLAB program, using the LLR-BP decoding algorithm, please correct me. Otherwise in accordance with GB-generated matrix and calibration matrix generation later Chuan-up
Platform: | Size: 1024 | Author: 权大广 | Hits:

[VHDL-FPGA-Verilog] DE2_TV

Description: 用于Altera公司DE2开发板的TV demonstration-Altera Corporation for DE2 development board of the TV demonstration
Platform: | Size: 140288 | Author: Morgan | Hits:

[VHDL-FPGA-Verilog] DE2_LCM_TV_PAL

Description: DE2上的基于FPGA视频开发资料第3部分-DE2 video
Platform: | Size: 269312 | Author: 刘志文 | Hits:

[VHDL-FPGA-Verilog] IR

Description: 红外线接收: 使用任何遥控器（电视、空调等），对准开发板的红外线接收管，按下遥控器的任何按钮，LED0 会按照红外线码进行闪烁。 -Infrared receiver: the use of any remote control (TV, air conditioning, etc.), targeting the development board infrared receiver tube, press any button on the remote control, LED0 will be in accordance with the infrared codes flashing.
Platform: | Size: 78848 | Author: panda | Hits:

[VHDL-FPGA-Verilog] 61EDA_C878

Description: fpga tv转vga 解码器adv7180，视频转换adv7123-fpga tv to vga，decoder adv7180，video converter adv7123
Platform: | Size: 2042880 | Author: james | Hits:

[Other] vga

Description: 电视机彩条发生器，有文字，图案等多种选择模式-TV Color Bar Generator, with text, patterns and other selection mode
Platform: | Size: 7168 | Author: ryoheihan | Hits:

[VHDL-FPGA-Verilog] DE2_TV

Description: 友晶公司DE2开发板的TV示例完整源代码 FPGA Cyclone-Friends of the crystal of TV company DE2 development board complete source code for FPGA CycloneII sample
Platform: | Size: 4076544 | Author: caizuhong | Hits:

[VHDL-FPGA-Verilog] LIP6301CORE_tv_filter

Description: TV Filter VHDL Souece code
Platform: | Size: 546816 | Author: jc | Hits:

[VHDL-FPGA-Verilog] dvbt_core_latest.tar

Description: The present document describes a baseline transmission system for digital terrestrial TeleVision (TV) broadcasting. It specifies the channel coding/modulation system intended for digital multi-programme LDTV/SDTV/EDTV/HDTV terrestrial services. -The present document describes a baseline transmission system for digital terrestrial TeleVision (TV) broadcasting. It specifies the channel coding/modulation system intended for digital multi-programme LDTV/SDTV/EDTV/HDTV terrestrial services.
Platform: | Size: 9881600 | Author: shen | Hits:

[VHDL-FPGA-Verilog] kongbao2

Description: 信道传输中所需的TS码流仿真包，数字电视的类似信号格式，VHDL编写，简单明了，希望对大家有帮助-The desired channel transmission simulation package TS stream, similar signal formats of digital TV, VHDL written, clear and simple, we want to help
Platform: | Size: 1024 | Author: 欧阳凯 | Hits:

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[VHDL-FPGA-Verilog] 9.16fifoasi

[matlab] ldpcdecoderandencoder

[VHDL-FPGA-Verilog] DE2_TV

[VHDL-FPGA-Verilog] DE2_LCM_TV_PAL

[VHDL-FPGA-Verilog] IR

[VHDL-FPGA-Verilog] 61EDA_C878

[Other] vga

[VHDL-FPGA-Verilog] DE2_TV

[VHDL-FPGA-Verilog] LIP6301CORE_tv_filter

[VHDL-FPGA-Verilog] dvbt_core_latest.tar

[VHDL-FPGA-Verilog] kongbao2

[VHDL-FPGA-Verilog] PAL

[VHDL-FPGA-Verilog] DE2_115_TV

[Software Engineering] FPGA

[VHDL-FPGA-Verilog] caitiao

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