Search - VHDL UART

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[VHDL-FPGA-Verilog] VHDL语言的UART串行接口芯片程序 DL : 1: VHDL语言的UART串行接口芯片程序
Update : 2009-07-09 Size : 16.72kb Publisher : redskier
[VHDL-FPGA-Verilog] 一个简单的UART DL : 1: 采用VHDL编写的一个简单的UART-using VHDL prepared a simple UART
Update : 2025-02-17 Size : 3kb Publisher : 陈旭
[VHDL-FPGA-Verilog] uart from opencores DL : 0: 用VHDL实现串口可以实现与pc机的通信收发中断都可以效果比较好-VHDL implement serial port, it can communicate with pc, it can accept and send message, and it can be interrupted.
Update : 2025-02-17 Size : 9kb Publisher : 熊明
[Documents] UART(FPGA) DL : 0: 基于FPGA的串行通信UART控制器，采用VHDL语言编写，包含多个子模块。在ISE或FPGA的其它开发环境下新建一个工程，然后将文档中的各个模块程序添加进去，即可运行仿真。源程序已经过本人的仿真验证。-FPGA-based UART serial communication controller, using VHDL language, includes a number of sub-module. ISE FPGA or in the other developing a new environment, then documentation of the various modules of procedures added to it, will be running simulation. I have been the source of the simulation.
Update : 2025-02-17 Size : 14kb Publisher : 李浩
[VHDL-FPGA-Verilog] uart-verilog-vhdl DL : 0: 拿verilog和vhdl编写的串口通信代码(可综合)-with vhdl and verilog prepared by the serial communication code (synthesis)
Update : 2025-02-17 Size : 288kb Publisher : 刘索山
[VHDL-FPGA-Verilog] VHDL_UART DL : 0: VHDL语言的UART串行接口芯片程序,仅供学习使用-VHDL UART serial interface chip procedure is for learning
Update : 2025-02-17 Size : 4kb Publisher : MINGER
[Linux-Unix] UART DL : 0: 自己用VHDL写的一个串口程序，调试成功，并且用到了项目中，希望初学者可以借鉴下-Their use VHDL to write a serial program, debug the success of the project and used in the hope that beginners can learn from the next
Update : 2025-02-17 Size : 299kb Publisher : yanglei
[VHDL-FPGA-Verilog] URATVHDLDocument DL : 0: 用VHDL描述uart后整理的文档，很全面，代码注释很详细-Described using VHDL UART finishing the document, very comprehensive and very detailed code Notes
Update : 2025-02-17 Size : 53kb Publisher : ninghuiming
[VHDL-FPGA-Verilog] uart DL : 0: vhdl书写uart代码,经验证功能非常的全.-UART code written in VHDL, experience card features a very wide.
Update : 2025-02-17 Size : 396kb Publisher : zjc
[VHDL-FPGA-Verilog] uart(serial)-200792511240998 DL : 0: 基于vhdl 的串行接口具有完整的程序-VHDL-based serial interface with a complete process
Update : 2025-02-17 Size : 259kb Publisher : weixing
[VHDL-FPGA-Verilog] uart DL : 0: 串口通讯协议，你您可以自己建个工程，再将需要的VHDL文本，添加到工程中，理解程序在仿真！-Serial communication protocol, you can build your project, and then need VHDL text, added to the project, understand the procedures in the simulation!
Update : 2025-02-17 Size : 10kb Publisher : 张亚伟
[VHDL-FPGA-Verilog] VHDL-XILINX-EXAMPLE26 DL : 0: [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][6--8位并入串出寄存器][7--内部三态总线][8--含清零和同步时钟使能的4位加法计数器][9--数控分频器][10--4位十进制频率计][11--译码扫描显示电路][12--用状态机实现序列检测器的设计][13--用状态机对ADC0832电路控制实现SIN函数发生器][14--用状态机实现ADC0809的采样电路设计][15--DMA方式A/D采样控制电路设计][16--硬件电子琴][17--乐曲自动演奏][18--秒表][19--移位相加8位硬件乘法器][20--VGA图像显示控制器(彩条)][21--VGA图像显示控制器][22--等精度频率计][23--模拟波形发生器][24--模拟示波器][25--通用异步收发器(UART)][26--8位CPU设计(COP2000)]
Update : 2025-02-17 Size : 3.52mb Publisher : hawd
[Com Port] uart DL : 0: 开源的串口通信程序，用vhdl 编写的，已通过测试，在DE2的开发板上能够运行。-Open source serial communication procedures, prepared by using VHDL, has been tested in the DE2 development board to run.
Update : 2025-02-17 Size : 2kb Publisher : caijl88
[VHDL-FPGA-Verilog] uart DL : 0: vhdl语言编写的实现uart协议的程序,用于rs232电气接口程序开发.支持比特率从2400-115200.-VHDL languages realize UART protocol procedures, electrical RS232 interface for program development. to support the bit rate from 2400-115200.
Update : 2025-02-17 Size : 5kb Publisher : 陈想
[VHDL-FPGA-Verilog] uart DL : 0: VHDL编写的异步通信串行口设计用Quartus工具编译-VHDL prepared the design of serial asynchronous communication tool used Quartus compiler
Update : 2025-02-17 Size : 208kb Publisher : 朱兆斌
[VHDL-FPGA-Verilog] UART DL : 0: 经典UART程序，通用异步收发器设计的vhdl语言-UART classical procedures, UART VHDL design language
Update : 2025-02-17 Size : 6kb Publisher : yu_leo
[SCM] new-lins-uart-all DL : 0: 无私奉献，VHDL 源码，用于实现FPGA上的UART(串口控制器)，可以实现FPGA与单片机，PC机的串口通讯。-Selfless dedication, VHDL source code for the FPGA realization of the UART (serial port controller), you can realize FPGA and MCU, PC serial communication machine.
Update : 2025-02-17 Size : 6kb Publisher : 骑士
[Communication-Mobile] uart DL : 0: 这个是UART的控制器，已经跑通过，分4个模块，波特率生成、发送、接收和fifo,可供初学者参考-This is the UART controller, has been run through, sub-4 module, baud rate generating, sending, receiving and fifo, for beginners reference
Update : 2025-02-17 Size : 3kb Publisher : duan
[VHDL-FPGA-Verilog] UART DL : 0: 用FPGA实现了RS232异步串行通信，所用语言是VHDL，另外本人还有Verilog的欢迎交流学习，根据RS232 异步串行通信来的帧格式，在FPGA发送模块中采用的每一帧格式为：1位开始位+8位数据位+1位奇校验位+1位停止位，波特率为2400。由设置的波特率可以算出分频系数，具体算法为分频系数X=CLK/(BOUND*2)。-Using FPGA to achieve the RS232 asynchronous serial communication, the language used is VHDL, In addition, I also welcome the exchange of learning Verilog, according to RS232 asynchronous serial communication to the frame format, in the FPGA module used to send each frame format : the beginning of a bit+ 8-bit data bit+ 1 bit odd parity bit+ 1 bit stop bit, baud rate for 2400. By setting the baud rate can be calculated at the frequency coefficient, the specific algorithm for the sub-frequency coefficient X = CLK/(BOUND* 2).
Update : 2025-02-17 Size : 1kb Publisher : saibei007
[VHDL-FPGA-Verilog] Uart DL : 0: 用ＦＰＧＡ，VHDL实现的Uart核，quartusII完整工程，实用-Using FPGA, VHDL realize the UART core, quartusII complete projects, practical
Update : 2025-02-17 Size : 617kb Publisher : wanyou

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