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[Windows Develop] MC-ACT-RSENC_DS

Description: MemecCoreReed-Solomon coding is a method of forward error correction in the form of block coding. Block coding consists of calculating a number of parity symbols over a number of message symbols. The parity symbols are appended to the end of the message symbols forming a codeword. Reed-Solomon coding is described in the form RS(n,k), where k is the number of message symbols in each block and n is the total number of symbols in the codeword. The value t defines the number of symbols that can be corrected by the Reed-Solomon code, where t=(n-k)/2 and the number of parity symbols is equal to 2t.
Platform: | Size: 95232 | Author: 张波 | Hits:

[VHDL-FPGA-Verilog] OFDMcode

Description: OFDM 的 VHDL 实现 分块实现. 功能强大 -OFDM block of VHDL realize realize. Powerful
Platform: | Size: 38912 | Author: 付文强 | Hits:

[VHDL-FPGA-Verilog] DS_FH

Description: 扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现-Frequency-hopping communication QUARTUS7.0 expanded development environment in the VHDL source code and the achievement of the overall block diagram
Platform: | Size: 2278400 | Author: Rebecca | Hits:

[Voice Compress] yuyintongxin

Description: 基于CPLD的语音通信系统设计与实现毕业设计 原版包括程序源码，各部分仿真图，框图-CPLD-based voice communications system design and implementation of the design of the original graduate program, including source code, the part of simulation diagram, block diagram
Platform: | Size: 3988480 | Author: 李卫东 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 本代码为用VHDL语言设计实现加法器、减法器、乘法器，并提供了模块图，进行了波形仿真。-This code is for the use of VHDL Language Design and Implementation of adder, subtracter, multiplier, and provides a block diagram carried out a wave simulation.
Platform: | Size: 15360 | Author: 张霄 | Hits:

[Windows Develop] haiming

Description: 信息论与编码中，实现的一个简单的（7,4）系统线性分组码，也即海明码-Construct a systematic (7,4) linear block code.You can use c lauguage or HDL (VHDL or Verilog-HDL) to describe it. Construct a linear block decoder,and decode the received code vector[0 1 0 1 1 0 1].Please write the detail of how to realize it in computer lauguage.And list the program lines.
Platform: | Size: 1024 | Author: 周一 | Hits:

[VHDL-FPGA-Verilog] CRCDecoding

Description: CRC检错程序。只能检错不能纠错。（40,32）的分组码检错，反馈函数：x8+x7+x4+x3+x+1-CRC error detection process. Not only error detection correction. (40,32) and block code error detection, feedback function: x8+ x7+ x4+ x3+ x+1
Platform: | Size: 147456 | Author: 李雪茹 | Hits:

[VHDL-FPGA-Verilog] code(opp)

Description: vhdl语言实现线性分组码的编码以及解码-vhdl language of linear block code encoding and decoding
Platform: | Size: 1024 | Author: kid | Hits:

[VHDL-FPGA-Verilog] vhdl-implementation-of-cordic-algorithm-for-wirel

Description: OFDM system model and Block diagram of CORDIC algorithm using FPGA VHDL code -OFDM system model and Block diagram of CORDIC algorithm using FPGA VHDL code
Platform: | Size: 395264 | Author: | Hits:

[VHDL-FPGA-Verilog] RAM_BLOCK

Description: Ram block code in Verilog
Platform: | Size: 25600 | Author: M. Usman | Hits:

[assembly language] vhdl

Description: 译码器设计 实现3-8译码器的门级和行为级设计；完成3-8译码器的门级和行为级设计的仿真，并下载到开发板进行验证。 用拨挡开关K1，K2，K3作为输入的三位二进制码，输出的8位码分别用LED1~LED8 显示-Achieve 3-8 decoder gate-level and behavioral level design complete the 3-8 decoder gate-level simulation and behavioral level design, and downloaded to the development board for verification. Using DIP switch block K1, K2, K3 of the three binary code as input, output 8 yards respectively show LED1 ~ LED8
Platform: | Size: 265216 | Author: 阮智钦 | Hits:

[VHDL-FPGA-Verilog] myfpga

Description: 详细描述设计过程 ① 指令格式设计 ② 微操作的定义 ③ 节拍的划分 ④ 处理器详细结构设计框图及功能描述(评分重点) a. 模块之间的连线单线用细线，2根及以上用粗线并标出根数及. b. 用箭头标明数据流向,例化时用到的信号名称应标在连线上 ⑤ 各功能模块结构设计框图及功能描述（评分重点） ⑥ VHDL代码、UCF文件、测试指令序列（每条指令的含义） ⑦ 实验总结，在调试和下载过程中遇到的问题 -Design Process Design ② ① instruction format defined micro-operation ③ ④ processor division beat a detailed description of the structural design and function block diagram (score focus) a detailed description single wire connection between modules with thin lines, 2 and above with crude line and mark the number and. b. Use the arrow indicating the flow of data, signal names used in cases of functional modules shall be marked ⑤ structural design diagram and functional description (score focus) ⑥ VHDL code on connection, UCF file test instruction sequence (the meaning of each instruction) ⑦ experiments summarized in debugging and downloading problems encountered in the process
Platform: | Size: 6259712 | Author: 王思雨 | Hits:

[VHDL-FPGA-Verilog] lab6

Description: 详细描述设计过程和实验中遇到的问题，包括： ① 指令格式设计 ② 微操作的定义 ③ 节拍的划分 ④ 处理器详细结构设计框图及功能描述(评分重点) a. 模块之间的连线单线用细线，2根及以上用粗线并标出根数及. b. 用箭头标明数据流向,例化时用到的信号名称应标在连线上 ⑤ 各功能模块结构设计框图及功能描述（评分重点） ⑥ VHDL代码、UCF文件、测试指令序列（每条指令的含义） 实验总结，在调试和下载过程中遇到的问题 -A detailed description of the design process and problems encountered in the experiment, including:. ① ② micro-operation instruction format design definition ③ ④ processor division beat detailed description of the structural design and function block diagram (score focus) a single-wire connection between modules with a thin, two more than the number indicated by bold lines and and. b. Use the arrow indicating the flow of data, signal names used when instantiated ⑤ shall be marked on the connection of each functional module design and function block diagram and description (Ratings Key) ⑥ VHDL code, UCF file, test instruction sequence (the meaning of each instruction) experiments summarized problems encountered during commissioning and download the
Platform: | Size: 5848064 | Author: 王思雨 | Hits:

[VHDL-FPGA-Verilog] PWM-IS

Description: control Pulse width modulation (PWM) using VHDL code and Block schematic.the selection switch at the FPGA board is important to control the duty cycle of PWM.For example application that can be used is to control speed dc motor.-control Pulse width modulation (PWM) using VHDL code and Block schematic.the selection switch at the FPGA board is important to control the duty cycle of PWM.For example application that can be used is to control speed dc motor.
Platform: | Size: 1931264 | Author: abdul | Hits:

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