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[SourceCode] DDR（双速率）SDRAM控制器参考设计VHDL代码

Description: SDRAM的控制程序很复杂，这个对大家肯定有帮助！
Platform: | Size: 1022145 | Author: zsy5460 | Hits:

[SourceCode] SDR-SDRAM-vhdl

Description: SDR-SDRAM-vhdl单个SDRAM的控制，通过它可以学习了解SDRAM的时序等，很有帮助哦 ！
Platform: | Size: 717771 | Author: zsy5460 | Hits:

[SourceCode] altera sdram controller

Description: altera sdram controller vhdl
Platform: | Size: 2365413 | Author: langzhongfeilang@126.com | Hits:

[VHDL-FPGA-Verilog] sdram_vhd_134

Description: Xilinx Sdram控制器VHDL源代码-Sound code of Xilinx Sdram Controller based on VHDL
Platform: | Size: 54272 | Author: 刘汉忠 | Hits:

[VHDL-FPGA-Verilog] sdram_vhdl_lattice

Description: lattice sdram 控制器VHDL源代码-Sound code of Lattice Sdram Controller based on VHDL
Platform: | Size: 180224 | Author: 刘汉忠 | Hits:

[VHDL-FPGA-Verilog] ref-ddr-sdram-vhdl

Description: 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
Platform: | Size: 1031168 | Author: 包盛花 | Hits:

[VHDL-FPGA-Verilog] Verilog&Vhdl混语言对SDRAM的控制源代码

Description: Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!
Platform: | Size: 249856 | Author: 飞扬 | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl

Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Platform: | Size: 776192 | Author: 张涛 | Hits:

[Other] ref-ddr-sdram-vhdl

Description: 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
Platform: | Size: 437248 | Author: kevin | Hits:

[Documents] SDRAM-VHDL

Description: SDRAM控制器的VHDL实现，pdf格式，有需要多的，联系我-SDRAM controller VHDL, pdf format, it needs more, Contact
Platform: | Size: 124928 | Author: | Hits:

[Other] ref-sdr-sdram-vhdl

Description: FPGA连接SDRAM的源程序，VHDL语言实现，功能基本完全。应用效果好。-FPGA connected SDRAM source, VHDL language, the basic function fully. Application effective.
Platform: | Size: 732160 | Author: young | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: 基于FPGA的SDRAM控制器的设计和实现,还比较好勒.-FPGA-based SDRAM controller design and realization, but also better le.
Platform: | Size: 69632 | Author: rubyshirial | Hits:

[VHDL-FPGA-Verilog] sdram

Description: sdram test controller altera -sdram test controller altera
Platform: | Size: 1519616 | Author: yangchun | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-verilog

Description: SDRAM的vegilog代码，做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM
Platform: | Size: 717824 | Author: 吴厚航 | Hits:

[VHDL-FPGA-Verilog] ref-ddr-sdram-vhdl

Description: 基于VHDL编写的DDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the DDR-SDRAM controller programming, is currently the industry s commonly used RAM controller
Platform: | Size: 1031168 | Author: wfs | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl

Description: 基于VHDL编写的SDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the SDR-SDRAM controller programming, is now commonly used in industry RAM controller
Platform: | Size: 1013760 | Author: wfs | Hits:

[VHDL-FPGA-Verilog] vga_core(vhdl)

Description: vga视频输出（vhdl），主要是从sdram中产生图形，输出到vga中-vga video outputs [vhdl], mainly arising from the SDRAM graphics, output to vga Medium
Platform: | Size: 459776 | Author: 程荣 | Hits:

[Other] SDR-SDRAM-ctl1

Description: SDR SDRAM控制器，FPGA vhdl代码-SDR SDRAM Controller
Platform: | Size: 718848 | Author: | Hits:

[VHDL-FPGA-Verilog] sdram

Description: 程序说明: 本次实验控制开发板上面的SDRAM完成读写功能。 先向SDRAM里面写数据，然后再将数据读出来做比较，如果不匹配就通过LED变亮显示出来，如果一致，LED就不亮。 part1是使用Modelsim仿真的工程 part2是在开发斑上面验证的工程 目录说明: part1: part1_32是4m32SDRAM的仿真工程 part1_16是4m16SDRAM的仿真工程 \model文件夹里面是仿真模型 \rtl文件夹里面是源文件 \sim文件夹里面是仿真工程 \test_bench文件夹里面是测试文件 \wave文件夹里面是仿真波形 -Procedure Note: In this experiment, control development board to complete the above SDRAM read and write capabilities. SDRAM write data inside first and then read out the data to compare, if you do not match on the adoption of LED variable light display, if agreed, LED does not light. part1 is to use Modelsim simulation project part2 the top spot verification in the development of the project directory Description: part1: part1_32 is 4m32SDRAM simulation project part1_16 is 4m16SDRAM simulation works \ model folder, which is a simulation model \ rtl folder, which is the source file \ sim is a simulation project inside the folder \ test_bench folder which is a test file \ wave inside the folder is a simulation waveform
Platform: | Size: 779264 | Author: 军军 | Hits:

[VHDL-FPGA-Verilog] sdram-source

Description: SDR SDRAM 控制器的源代码 altera公司的-source code from altera
Platform: | Size: 717824 | Author: wela | Hits:
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