Search - Verilog Modulation

Search - Verilog Modulation - List

[VHDL-FPGA-Verilog] signal DL : 0: 产生sinx＋cosx波形用于正交调制得测试信号一次输出正交和同相分量 verilog语言-Sinx cosx generate quadrature modulation waveforms for a test signal and an output quadrature-phase component with the Verilog language
Update : 2025-02-17 Size : 225kb Publisher : 杨洁
[Communication] 16pam DL : 0: 用VERILOG语言实现16QAM的数字调制的程序，已经在ISE10.1版本中调试通过-Using Verilog language realize 16QAM digital modulation procedures are in the debug version ISE10.1 through
Update : 2025-02-17 Size : 7.33mb Publisher : 王莉
[VHDL-FPGA-Verilog] AM DL : 0: FPGA内AM调制工程。内带调制波、载波生成。关键词：FPGA verilog AM DDS-AM modulation works within the FPGA. Within the band modulation wave generated carrier. Key words: FPGA verilog AM DDS
Update : 2025-02-17 Size : 1.61mb Publisher : baixiangzhou
[VHDL-FPGA-Verilog] Verilog_example_of_pulse_width_modulation DL : 0: 学习verilog的一些资料。是脉宽调制控制的题目，以及源码和仿真文件。感觉代码风格还不错，可以学习一下。-Verilog study some of the information. Pulse width modulation control are the subject, as well as the source code and simulation files. Feel good style of code, you can study about.
Update : 2025-02-17 Size : 6.01mb Publisher : nothing
[VHDL-FPGA-Verilog] 16qam——modulation DL : 0: verilog编写的16qam调制程序，将所有东西装入工程，运行mmm16主程序。其中载波为一个周期采十个点，并乘以2^8-1取整数。在quartusII运行通过。-verilog modulation procedures 16qam prepared all things into works mmm16 to run the main program. One carrier for a cycle of 10 points taken, and multiplied by an integer from 2 ^ 8-1. Running through the quartusII.
Update : 2025-02-17 Size : 5kb Publisher : 王力宏
[source in ebook] VHDL DL : 0: 16QAM调制器的Verilog HDL程序，可以实现16QAM调制-16QAM modulator Verilog HDL procedures, 16QAM modulation can be achieved
Update : 2025-02-17 Size : 1kb Publisher : 吴丹
[GPS develop] PcodeGeneration DL : 0: 在ModelSim或其他支持Verilog语言编译的环境中仿真可得GPS的P码及与卫星数据码调制后的波形，其中一个为源程序，另一个为测试程序-ModelSim or other support in the language Verilog simulation environment to compile available GPS P-code and code of satellite data after the modulation waveform, one for the source, and the other for the test procedure
Update : 2025-02-17 Size : 68kb Publisher : tianjieyu
[VHDL-FPGA-Verilog] MPSK DL : 0: MPSK调制与解调系统设计和VHDL程序与仿真-MPSK modulation and demodulation system design and simulation of VHDL procedures and
Update : 2025-02-17 Size : 78kb Publisher : jack wolf
[VHDL-FPGA-Verilog] module_dem DL : 1: 用verilog编写的信号调制解调程序，包括ask,fsk,qpsk的fpga实现-Prepared using verilog signal modulation and demodulation process, including ask, fsk, qpsk of fpga implementation
Update : 2025-02-17 Size : 5.79mb Publisher : yu
[VHDL-FPGA-Verilog] 50846288C DL : 0: verilog 硬件编程实现bpsk调制-verilog hardware, programming bpsk Modulation
Update : 2025-02-17 Size : 50kb Publisher : 凡要林
[Post-TeleCom sofeware systems] qam_64 DL : 0: 64QAM调制,采用硬件语言verilog实现,其中调用了DDS的IP核-64QAM modulation, using language verilog hardware implementation, which is called the IP core of the DDS
Update : 2025-02-17 Size : 1kb Publisher : zhujing
[VHDL-FPGA-Verilog] FFT DL : 0: Verilog实现的FFT模块，供OFDM调制系统使用，可供大家参考学习-Verilog implementation FFT module for the OFDM modulation system used for your reference study
Update : 2025-02-17 Size : 1.17mb Publisher : 梁贵轩
[VHDL-FPGA-Verilog] FSK_MOD_my DL : 0: verilog语言设计的用于fsk调制的源码-verilog language design for fsk modulation source
Update : 2025-02-17 Size : 222kb Publisher : 咕嘟大树
[VHDL-FPGA-Verilog] dds_final DL : 1: 使用Verilog HDL语言实现的一个DDS，可以发生0-10Mhz正弦波、方波、三角波，频率步进可调，FM调制、AM调制，调制度可调。DA芯片为8位并行，160MHz-Using the Verilog HDL language implementation of a DDS, can occur 0-10Mhz sine, square, triangle wave, frequency step tunable, FM modulation, AM modulation, adjustable modulation. DA-chip 8-bit parallel, 160MHz
Update : 2025-02-17 Size : 1.56mb Publisher : nostalgia
[VHDL-FPGA-Verilog] qpsk_module DL : 1: 采用Verilog语言编写了一个qpsk调制的程序-Verilog language using a modulation process qpsk
Update : 2025-02-17 Size : 311kb Publisher : inves
[Communication] examples DL : 0: 二进制差分编码解码，二进制差分相移键控二进制幅移键控，二进制相移键控，二进制频移键控最小频移键控的调制与解调-Differential encoding and decoding binary, binary differential phase shift keying binary amplitude shift keying, BPSK, binary frequency shift keying Minimum Shift Keying modulation and demodulation
Update : 2025-02-17 Size : 5kb Publisher : xvlu
[VHDL-FPGA-Verilog] DSB3 DL : 0: 利用ISE软件编写的Verilog程序，可以进行信号的双边带调制-Using ISE software program written in Verilog, can be bilateral with a modulation signal
Update : 2025-02-17 Size : 920kb Publisher : 蜡笔
[VHDL-FPGA-Verilog] psk DL : 0: 应用verilog语言编写实现二元相移键控调制过程-Application verilog language to achieve binary phase shift keying modulation
Update : 2025-02-17 Size : 3kb Publisher : king
[VHDL-FPGA-Verilog] ofdm DL : 0: ofdm调制解调的fpga实现。使用Verilog实现IEEE 802.16a系统的调制解调模块。-ofdm modulation and demodulation of fpga implementation. Verilog implementation using IEEE 802.16a system, modem module.
Update : 2025-02-17 Size : 2kb Publisher : 张维
[assembly language] MSK DL : 0: 用VERILOG编写的MSK调制模块的程序代码简单易懂-MSK modulation with a VERILOG module written in easy to understand code
Update : 2025-02-17 Size : 1.92mb Publisher : 龙兰飞

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