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Description: 这是一个rs译码器的verilog程序运行于quatus-This is a rs decoder running on Verilog quatus
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Size: 132096 |
Author: yuanfeng |
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Description: 这是rs(255,223)编码的verilog源程序。里面有:encode、decode、test-bench等文件。-This is rs (255,223) verilog source coding. Inside : encode, decode, test-bench and other documents.
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Size: 18394 |
Author: 陈 |
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Description: encode.v The encoder
syndrome.v Syndrome generator in decoder
berlekamp.v Berlekamp algorithm in decoder
chien-search.v Chien search and Forney algorithm in decoder
decode.v The top module of the decoder
inverse.v Computes multiplication inverse of an Galois field element
test-bench.v The test fixture, and some brief notes on using the modules.
data-rom.v A simple data source for testing
run For those intelligence-challenged who can t run verilog
LGPL The license
-encode.v syndrome.v Syndrome generator in decoder al berlekamp.v Berlekamp gorithm in decoder chien - search.v Chien searc h and Forney in decoder algorithm decode.v The t op module of the decoder inverse.v Computes intercommunication tiplication inverse of an element over Galois field test-bench.v The test fixture. and some brief notes on using the modules. data - rom.v A simple data source for testing run For th PNA intelligence-challenged who can not run veri The log LGPL license
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Size: 44917 |
Author: zs8292 |
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Description: 曼彻斯特编解码Verilog代码 .zip-Manchester codec Verilog code. Zip
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Size: 10240 |
Author: 崔广辉 |
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Description: 这是一个rs译码器的verilog程序运行于quatus-This is a rs decoder running on Verilog quatus
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Size: 133120 |
Author: yuanfeng |
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Description: 高品质音频编解码器WM8731的Verilog使用程序。-high-quality audio codec WM8731 Verilog procedures.
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Size: 7168 |
Author: 李全 |
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Description: 这是rs(255,223)编码的verilog源程序。里面有:encode、decode、test-bench等文件。-This is rs (255,223) verilog source coding. Inside : encode, decode, test-bench and other documents.
Platform: |
Size: 18432 |
Author: 陈 |
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Description: encode.v The encoder
syndrome.v Syndrome generator in decoder
berlekamp.v Berlekamp algorithm in decoder
chien-search.v Chien search and Forney algorithm in decoder
decode.v The top module of the decoder
inverse.v Computes multiplication inverse of an Galois field element
test-bench.v The test fixture, and some brief notes on using the modules.
data-rom.v A simple data source for testing
run For those intelligence-challenged who can t run verilog
LGPL The license
-encode.v syndrome.v Syndrome generator in decoder al berlekamp.v Berlekamp gorithm in decoder chien- search.v Chien searc h and Forney in decoder algorithm decode.v The t op module of the decoder inverse.v Computes intercommunication tiplication inverse of an element over Galois field test-bench.v The test fixture. and some brief notes on using the modules. data- rom.v A simple data source for testing run For th PNA intelligence-challenged who can not run veri The log LGPL license
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Size: 45056 |
Author: zs8292 |
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Description: 用verilog语言实现DCT编解码
附有DCT的说明-Using Verilog language realize DCT codec with a description of DCT
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Size: 65536 |
Author: 周韧研 |
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Description: 曼彻斯特编解码Verilog代码 非常好的 速度快,而且资源占用少。
-Manchester codec Verilog code very good speed, but also occupy less resources.
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Size: 10240 |
Author: 王鹏 |
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Description: (2,1,9)卷积编解码器,译码部分采用Vitebi译码算法,设计使用Verilog HDL语言,在Modelsim平台下仿真通过-(2,1,9) convolutional codec, decoding part decoding algorithm used Vitebi design using Verilog HDL language simulation in ModelSim platform through
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Size: 10240 |
Author: rxl |
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Description: 关于通信原理课程设计中HDB3编解码的一个VERILOG源代码-Principles of curriculum design on the communications HDB3 codec in a Verilog source code
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Size: 150528 |
Author: 小亮 |
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Description: RS[255,223]纠错码verilog源码,包含编码和解码模块,以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
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Size: 27648 |
Author: 饶进平 |
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Description: 用verilog写的一个manchester code的代码,含编解码-Used to write a verilog code for manchester code containing codec
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Size: 9216 |
Author: stream |
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Description: rs编解码的verilog实现源代码,从硬件实现rs的编解码-rs codec to achieve the verilog source code, from the hardware codec rs
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Size: 101376 |
Author: 曹晶 |
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Description: 1553B编解码程序
verilog 描述-1553B codec procedures described in verilog
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Size: 31744 |
Author: pan |
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Description: RFID系统的IEEE的文章,安全协议,认证-
In this paper, we first propose a cryptographic
authentication protocol which meets the privacy
protection for tag bearers, and then a digital Codec for
RFID tag is designed based on the protocol. The
protocol which uses cryptographic hash algorithm is
based on a three-way challenge response
authentication scheme.
In addition, we will show how the three different
types of protocol frame formats are formed by
extending the ISO/IEC 18000-3 standard[3] for
implementing the proposed authentication protocol in
RFID system environment. The system has been
described in Verilog HDL and also synthesized using
Synopsys Design Compiler with Hynix 0.25 µ m
standard-cell library. From implementation results, we
found that the proposed scheme is well suite to
implement robust RFID system against active attacks
such as the man-in-the-middle attack.
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Size: 233472 |
Author: fxy |
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Description: 是用VERILOG HDL和NIOS II C/C++ 编的DE2-70板子的音频编解码芯片的使用工程-Is VERILOG HDL and NIOS II C/C++ code of the DE2-70 board in the audio codec chip, the use of project
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Size: 21566464 |
Author: 覃建策 |
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Description: audio codec data sheet
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Size: 679936 |
Author: Venky |
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Description: verilog hdl实现5B6B编译码(光纤通信线路码型),包含了时钟发生器模块 ,信号源模块 ,编码模块 ,译码模块, 和检错模块,并通过modesim仿真验证。-verilog hdl achieve 5B6B encoding and decoding (code-based fiber-optic communication lines), contains a clock generator module, signal source modules, code modules, decoding module, and error detection module, and through modesim simulation.
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Size: 4096 |
Author: 林海全 |
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