Search - Verilog detector

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[VHDL-FPGA-Verilog] 1_061115131201 DL : 0: 数字边沿鉴相器 verilog源程序 -figures for 2500 phase-2500 verilog source digital phase detector verilog source
Update : 2025-02-17 Size : 9kb Publisher : mingming
[VHDL-FPGA-Verilog] src DL : 0: 一个SDH中最基本传输模块STM-1的帧头检测器，verilog编程实现-A basic SDH transmission module STM-1 Header detector, verilog Programming
Update : 2025-02-17 Size : 3kb Publisher : fredyu
[VHDL-FPGA-Verilog] 1111 DL : 0: 基于Verilog-HDL的转子振动噪声电压峰值检测，值得学习啊，-Verilog-HDL based on the rotor vibration noise voltage peak detector, it is worth learning ah,
Update : 2025-02-17 Size : 2.19mb Publisher : 王朱忠
[VHDL-FPGA-Verilog] detect DL : 0: 一个序列检测器的设计。程序不是问题，关键是理解状态机的编程思想。-A sequence detector design. Procedure is not a problem, the key is to understand the thinking of state machine programming.
Update : 2025-02-17 Size : 1kb Publisher : chengpan
[VHDL-FPGA-Verilog] check DL : 1: 用Verilog实现的序列检测器，可以检测出任意规定序列-Verilog implementation using the sequence detector
Update : 2025-02-17 Size : 3kb Publisher : huhahuha
[Other] chA DL : 1: phase frequency detector verilog
Update : 2025-02-17 Size : 13kb Publisher : kdlee
[VHDL-FPGA-Verilog] sequencedetector DL : 0: verilog code for 3 bit sequence detector
Update : 2025-02-17 Size : 500kb Publisher : anup
[ELanguage] synchronisation DL : 0: This circuit is a nice edge detector that gives you synchronous notification of edges on your input signal. There s no excuse for not doing this it s a tiny circuit in just five lines of Verilog.-This circuit is a nice edge detector that gives you synchronous notification of edges on your input signal. There s no excuse for not doing this it s a tiny circuit in just five lines of Verilog.
Update : 2025-02-17 Size : 39kb Publisher : Bhoumik Shah
[VHDL-FPGA-Verilog] 10010 DL : 0: Verilog状态机设计-10010序列检测器-Verilog state machine design-10010 Sequence Detector
Update : 2025-02-17 Size : 1kb Publisher : txj
[3G develop] Verilog_module DL : 1: Verilog编写基于FPGA的鉴相器模块-Write Verilog FPGA-based phase detector module
Update : 2025-02-17 Size : 447kb Publisher : zhh
[VHDL-FPGA-Verilog] seqdet DL : 0: 串行序列检测器，以得到modelsim仿真波形，用verilog编写。-Serial sequence detector to get modelsim simulation waveform, prepared with verilog.
Update : 2025-02-17 Size : 201kb Publisher : ll
[Algorithm] cordic_atan DL : 1: 用verilog语言实现计算反正切函数，在软件无线电中解调PM/FM中使用的尤为频繁。上传的压缩包是modelsim工程，基于6.5c,里边包含一个完整的PM波产生以及解调过程的matlab文件仿真，并取其中间的I和Q支路做为verilog文件的输入，并将其借条输出与MATLAB实际解调输出作比较。鉴相器的设计基于CORDIC算法，其精度取决于迭代的深度。由于工程实际运用只需要解调出atan值，并不需要绝对的值，所以并没有给予加权，需要的同学可以自己加上。-Calculated using verilog language arc tangent function, the software radio demodulation PM/FM is particularly used frequently. From the archive is modelsim project, based on 6.5c, inside the PM contains a complete demodulation process of wave generation and simulation matlab file, and whichever is the middle of the I and Q branch verilog file as input, and its IOU demodulated output and actual output of MATLAB for comparison. Phase detector design is based on CORDIC algorithm, its accuracy depends on the iteration depth. As the practical application of engineering demodulated atan value only and does not need absolute value, and there is no weight given to the need of the students can add their own.
Update : 2025-02-17 Size : 78kb Publisher : Jorge
[Other] seqdetector1001.v.tar DL : 0: 1001 sequence detector in verilog code for mealy state machine
Update : 2025-02-17 Size : 1kb Publisher : balu
[VHDL-FPGA-Verilog] top_module DL : 0: OFDM Gaurd Detector, Symbol length = 1024 & Gaurad Length = 256, and test bench written in verilog!
Update : 2025-02-17 Size : 3kb Publisher : apourbakhsh
[VHDL-FPGA-Verilog] dpll DL : 1: 基于Verilog的数字锁相环。包括三个模块，数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
Update : 2025-02-17 Size : 653kb Publisher : 栾帅
[VHDL-FPGA-Verilog] costas DL : 0: costas的verilog程序，包含乘法器，DDS，鉴相器，环路滤波器等模块-costas the verilog program, including multipliers, DDS, phase detector, loop filter modules
Update : 2025-02-17 Size : 6kb Publisher : 潇潇
[VHDL-FPGA-Verilog] detector DL : 0: this file is detector verilog source and test bench file thank you!
Update : 2025-02-17 Size : 108kb Publisher : choijinsol
[VHDL-FPGA-Verilog] sequential detector DL : 0: verilog 固定序列检测器，能够检测10111序列，波形无误。适合Verilog初学者学习(Verilog fixed sequence detector)
Update : 2025-02-17 Size : 7kb Publisher : 章荣
[VHDL-FPGA-Verilog] sequence detector DL : 0: sequence detector in verilog for xilinx
Update : 2025-02-17 Size : 185kb Publisher : addy007
[Embeded-SCM Develop] verilog状态机 DL : 0: 采用Verilog语言设计一个序列信号发生器和一个序列信号检测器，二者都以状态机模式实现。序列信号发生器输出8位宽度的序列信号“10110110”，通过数码管显示出来；序列信号发生器的输出接入序列信号检测器，检测器检测当前的输入信号，若出现目标序列信号则通过蜂鸣器输出一个声响，表示检测到有效的目标信号。(A sequence signal generator and a sequence signal detector are designed using Verilog language, both of which are implemented in a state machine mode. The sequence signal generator outputs an 8-bit wide sequence signal "10110110", which is displayed through the digital tube; the output of the sequence signal generator is connected to the sequence signal detector, the detector detects the current input signal, and if the target sequence signal appears, it passes through the bee. The horn emits a sound indicating that a valid target signal has been detected.)
Update : 2025-02-17 Size : 5.2mb Publisher : 听风吹雨

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