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Description: 码长1536 扩展因子64的 WIMAX的LDPC 编码器,支持5/6,2/3,3/4,3个码率,需要在顶层做参数修改
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Size: 225376 |
Author: mariojiang |
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Description: RS编码的源代码使用Verilog在Xinloinx平台-RS coding using the source code in Verilog Xinloinx platform
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Size: 5120 |
Author: 王锋 |
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Description: RS(32,28) encoder and decoder VHDL-RS (32,28) encoder and decoder VHDL
Platform: |
Size: 76800 |
Author: 王文 |
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Description: Quartus下的RS(5,3)编码器的源程序,用Verilog语言编写。-Quartus under the RS (5,3) encoder source code, using Verilog language.
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Size: 3072 |
Author: 桃子 |
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Description: 這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder-This is a two-dimensional lift-style 9/7 discrete wavelet of Verilog source code, this is Encoder
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Size: 7728128 |
Author: chiahao |
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Description: Verilog语言实现的Hamming(3,7)编码器,可用于FPGA实现-Verilog Language realize the Hamming (3,7) encoder, can be used to realize FPGA
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Size: 6144 |
Author: 陈楚龙 |
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Description: 循环码编码器verilog实现,里面包含有源程序和仿真图。-Cyclic code encoder Verilog realization, which contains the source code and simulation of Fig.
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Size: 15360 |
Author: 萍果 |
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Description: 这是一个verilog源码的优先编码器,可以通过led显示结果。-This is a Verilog source priority encoder, can be led through the result will be displayed.
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Size: 117760 |
Author: 王强 |
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Description: 8位优先编码器
verilog CPLD
EPM1270
源代码-8-bit priority encoder verilog CPLDEPM1270 source code
Platform: |
Size: 112640 |
Author: 韩思贤 |
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Description: JPEG encoder in Verilog
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Size: 41984 |
Author: megkel |
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Description: Verilog code for RS-(255,239) encoder.
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Size: 3072 |
Author: sharat |
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Description: Verilog jpec coder encoder source code
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Size: 283648 |
Author: Martin |
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Description: viterbi encoder and decoder
modeling verilog
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Size: 6144 |
Author: glory |
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Description: reed solomon encoder synthesis and simulation is done using verilog and working fine
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Size: 1126400 |
Author: priya |
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Description: verilog code for priority encoder
Platform: |
Size: 7168 |
Author: sandeep |
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Description: 曼彻斯特编解码源代码,还包含曼彻斯特码的说明文档-Manchester Encoder-Decoder
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Size: 40960 |
Author: cst008 |
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Description: 用Verilog实现卷积码(2,1,2)的编码器,采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the
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Size: 1024 |
Author: 吴雪 |
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Description: 11阶FIR滤波器和(7,4)编码器的Verilog语言,高手的作品,放心下-11-order FIR filter, and (7,4) encoder of the Verilog language, master' s works, rest assured that the next
Platform: |
Size: 2048 |
Author: 王刚 |
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Description: JPEG的編碼器
使用VERILOG以硬體實現
也使用MODEL模擬驗證-JPEG encoder using the VERILOG hardware implementation is also used to simulate authentication MODEL
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Size: 24576 |
Author: 林曉彬 |
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Description: ReedSolomon RS(15,11) Verilog 编码和解码测试程序 编码有两种实现方式 串行和并行方式(ReedSolomon RS(15,11) Verilog Encoder&Decoder)
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Size: 14336 |
Author: Ericxgj |
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