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[transportation applicationsverilog LDPC encoder

Description: 码长1536 扩展因子64的 WIMAX的LDPC 编码器,支持5/6,2/3,3/4,3个码率,需要在顶层做参数修改
Platform: | Size: 225376 | Author: mariojiang | Hits:

[ApplicationsRS encoder(Verilog)

Description: RS编码的源代码使用Verilog在Xinloinx平台-RS coding using the source code in Verilog Xinloinx platform
Platform: | Size: 5120 | Author: 王锋 | Hits:

[VHDL-FPGA-VerilogRS(32to28)encoderanddecoder

Description: RS(32,28) encoder and decoder VHDL-RS (32,28) encoder and decoder VHDL
Platform: | Size: 76800 | Author: 王文 | Hits:

[VHDL-FPGA-Verilogencode

Description: Quartus下的RS(5,3)编码器的源程序,用Verilog语言编写。-Quartus under the RS (5,3) encoder source code, using Verilog language.
Platform: | Size: 3072 | Author: 桃子 | Hits:

[Other97_2D_2Level

Description: 這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder-This is a two-dimensional lift-style 9/7 discrete wavelet of Verilog source code, this is Encoder
Platform: | Size: 7728128 | Author: chiahao | Hits:

[VHDL-FPGA-Veriloghamming.tar

Description: Verilog语言实现的Hamming(3,7)编码器,可用于FPGA实现-Verilog Language realize the Hamming (3,7) encoder, can be used to realize FPGA
Platform: | Size: 6144 | Author: 陈楚龙 | Hits:

[VHDL-FPGA-Verilogcrc_verilog

Description: 循环码编码器verilog实现,里面包含有源程序和仿真图。-Cyclic code encoder Verilog realization, which contains the source code and simulation of Fig.
Platform: | Size: 15360 | Author: 萍果 | Hits:

[SCM8bitencoder

Description: 这是一个verilog源码的优先编码器,可以通过led显示结果。-This is a Verilog source priority encoder, can be led through the result will be displayed.
Platform: | Size: 117760 | Author: 王强 | Hits:

[VHDL-FPGA-Verilog8ENCODE

Description: 8位优先编码器 verilog CPLD EPM1270 源代码-8-bit priority encoder verilog CPLDEPM1270 source code
Platform: | Size: 112640 | Author: 韩思贤 | Hits:

[Otherjpeg

Description: JPEG encoder in Verilog
Platform: | Size: 41984 | Author: megkel | Hits:

[VHDL-FPGA-Verilogrs_enc

Description: Verilog code for RS-(255,239) encoder.
Platform: | Size: 3072 | Author: sharat | Hits:

[VHDL-FPGA-Verilogverilog

Description: Verilog jpec coder encoder source code
Platform: | Size: 283648 | Author: Martin | Hits:

[Windows Mobileviterbi

Description: viterbi encoder and decoder modeling verilog
Platform: | Size: 6144 | Author: glory | Hits:

[VHDL-FPGA-Verilogreedsolomon

Description: reed solomon encoder synthesis and simulation is done using verilog and working fine
Platform: | Size: 1126400 | Author: priya | Hits:

[VHDL-FPGA-Verilog4x2_priorityencoder

Description: verilog code for priority encoder
Platform: | Size: 7168 | Author: sandeep | Hits:

[VHDL-FPGA-VerilogManchester

Description: 曼彻斯特编解码源代码,还包含曼彻斯特码的说明文档-Manchester Encoder-Decoder
Platform: | Size: 40960 | Author: cst008 | Hits:

[Communicationconv_vhdl

Description: 用Verilog实现卷积码(2,1,2)的编码器,采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the
Platform: | Size: 1024 | Author: 吴雪 | Hits:

[VHDL-FPGA-Verilog11FIRfliter

Description: 11阶FIR滤波器和(7,4)编码器的Verilog语言,高手的作品,放心下-11-order FIR filter, and (7,4) encoder of the Verilog language, master' s works, rest assured that the next
Platform: | Size: 2048 | Author: 王刚 | Hits:

[VHDL-FPGA-Verilogverilog-encoder

Description: JPEG的編碼器 使用VERILOG以硬體實現 也使用MODEL模擬驗證-JPEG encoder using the VERILOG hardware implementation is also used to simulate authentication MODEL
Platform: | Size: 24576 | Author: 林曉彬 | Hits:

[Communication-Mobilers_15_11

Description: ReedSolomon RS(15,11) Verilog 编码和解码测试程序 编码有两种实现方式 串行和并行方式(ReedSolomon RS(15,11) Verilog Encoder&Decoder)
Platform: | Size: 14336 | Author: Ericxgj | Hits:
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