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Description: 用CPLD控制图像卡进行帧存逻辑的verilog程序,用Quartus II 5.0打开-with CPLD control image frame buffer cards logical verilog procedures, Quartus II 5.0 Open
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Size: 1024 |
Author: 陈刚峰 |
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Description: 采用Verilog语言,实现了FPGA控制视频芯片的数据采集,并将数据按帧存储起来-Verilog language, to achieve control of the FPGA chip video data acquisition, Data will be stored up by frame
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Size: 1024 |
Author: margie |
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Description: 该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码，会用QUATUSII的人都应该知道如何使用，希望能给你带来帮助-The project is based on the language verilog hdl frame transmission protocol HDLC frame of this generation- Codes will be used QUATUSII people should know how to use, in the hope of giving you helpful
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Size: 382976 |
Author: 何丹萍 |
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Description: vga接口，摄像头，数码相框，都用到哦，快下载吧-vga interface, camera, digital photo frame, are used Oh, quick to download it
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Size: 2982912 |
Author: linchan |
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Description: 用FPGA实现了RS232异步串行通信，所用语言是VHDL，另外本人还有Verilog的欢迎交流学习，根据RS232 异步串行通信来的帧格式，在FPGA发送模块中采用的每一帧格式为：1位开始位+8位数据位+1位奇校验位+1位停止位，波特率为2400。由设置的波特率可以算出分频系数，具体算法为分频系数X=CLK/(BOUND*2)。-Using FPGA to achieve the RS232 asynchronous serial communication, the language used is VHDL, In addition, I also welcome the exchange of learning Verilog, according to RS232 asynchronous serial communication to the frame format, in the FPGA module used to send each frame format : the beginning of a bit+ 8-bit data bit+ 1 bit odd parity bit+ 1 bit stop bit, baud rate for 2400. By setting the baud rate can be calculated at the frequency coefficient, the specific algorithm for the sub-frequency coefficient X = CLK/(BOUND* 2).
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Size: 1024 |
Author: saibei007 |
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Description: SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhead bytes, it contains a lot of important information, the procedures for receiving SDH overhead processing, search header, sub-frequency ,勤務if E1 asynchronous byte fifo. Removable for three source code, I do not know the three procedures can be arrived
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Size: 6144 |
Author: 韩冰 |
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Description: TFT液晶屏驱动模块Verilog源码。实现方法：XC95288+K6R4008，K6R4008主要用作帧缓冲区，此模块仅支持256色-TFT LCD driver module Verilog source code. Realization: XC95288+ K6R4008, K6R4008 mainly used as a frame buffer, this module only supports 256 colors
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Size: 3072 |
Author: zhangming |
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Description: CMMB-GYT220.1(2006：传输部分，广播通信的帧结构、信道编码与调制).pdf
CMMB-GYT220.2(2006：复用部分，各种音视频，数据，ESG的复用方式).pdf
CMMB-GYT220.3(2007：业务部分，电子业务指南（ESG）的编辑和使用).pdf
CMMB-GYT220.4(2007：紧急广播).pdf
CMMB-GYT220.5(2008：数据广播，各种数据内容的打包封装格式).pdf
CMMB-GYT220.6(2008：条件接收，付费节目内容的控制方式).pdf
CMMB-GYT220.7(2008：接收终端，各种手机，PMP，电视棒，车载机的接收规范 ).pdf-CMMB-GYT220.1 (2006: transmission parts, radio communications frame structure, channel coding and modulation). Pdf CMMB-GYT220.2 (2006: reuse of a variety of audio and video, data, ESG Reuse way). pdf CMMB-GYT220.3 (2007: the business part of e-business guide (ESG) and the use of the editorial). pdf CMMB-GYT220.4 (2007: emergency radio). pdf CMMB-GYT220.5 (2008: data broadcasting, the types of data content of the package package format). pdf CMMB-GYT220.6 (2008: conditional access, pay-content control). pdf CMMB-GYT220.7 (2008: the receiving end, all kinds of mobile phones, PMP, TV rods, automotive machine receiving norms). pdf
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Size: 3057664 |
Author: 少 |
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Description: 同步技术的相关资料，里面有帧同步，字同步，位同步的实现方法-Synchronous technology related information, which there is frame synchronization, word synchronization, bit synchronization implementation Ways
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Size: 1798144 |
Author: qin |
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Description: 帧同步检测，verilog代码 是同步保护的经典范例-frame detection, verilog code
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Size: 1024 |
Author: leng |
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Description: H.264标准解码器全部verilog源码，包括帧内、帧间、变换编码、熵编码、滤波等所有模块-Standard H.264 decoder all verilog source, including intra-, inter-frame, transform coding, entropy coding, filtering all modules
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Size: 827392 |
Author: liu |
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Description: 基于Verilog语言的数字通信系统的帧同步的实现原理以及Verilog代码实现-Verilog language-based digital communications system, the realization of the principle of frame synchronization as well as the Verilog code
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Size: 481280 |
Author: 黄虎 |
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Description: uart串口传输的verilog RTL级源码，已通过仿真验证。文件主要包含发送、接受位处理，发送、接受字节帧处理，对学习串口通信的朋友很有帮助-uart serial transmission verilog RTL-level source code has been verified by simulation. File mainly contains the send, receive digital processing, sending, receiving bytes of frame processing, serial communications, a friend of learning helps
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Size: 7168 |
Author: 李鹏 |
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Description: RFID系统的IEEE的文章，安全协议，认证-
In this paper, we first propose a cryptographic
authentication protocol which meets the privacy
protection for tag bearers, and then a digital Codec for
RFID tag is designed based on the protocol. The
protocol which uses cryptographic hash algorithm is
based on a three-way challenge response
authentication scheme.
In addition, we will show how the three different
types of protocol frame formats are formed by
extending the ISO/IEC 18000-3 standard[3] for
implementing the proposed authentication protocol in
RFID system environment. The system has been
described in Verilog HDL and also synthesized using
Synopsys Design Compiler with Hynix 0.25 µ m
standard-cell library. From implementation results, we
found that the proposed scheme is well suite to
implement robust RFID system against active attacks
such as the man-in-the-middle attack.
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Size: 233472 |
Author: fxy |
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Description: H.264标准解码器全部verilog源码，包括帧内、帧间、变换编码、熵编码、滤波等所有模块和著名的6502的软件源码-The standard H.264 decoder all verilog source code, including the frame, frame, transform coding, entropy coding, filtering all modules and the famous 6502' s software source code
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Size: 75776 |
Author: 黄奇家 |
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Description: DE1上实现数码相框的verilog代码，以及实现方式-DE1 digital photo frame to achieve the verilog code, and Realization
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Size: 33127424 |
Author: roychen |
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Description: 详细介绍了7位巴克码以及帧同步，7位巴克码与帧同步的关系。-Details of the seven Barker code and frame synchronization, 7 Barker code and frame synchronization relationship.
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Size: 574464 |
Author: 杜伟 |
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Description: ofdm系统中的完整帧同步模块，基于verilog实现。-ofdm system full frame synchronization module, based on verilog implementation.
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Size: 571392 |
Author: 罗云 |
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Description: 本程序实现了PCM30的帧同步和失步检测，采用verilog编程，包含了工程文件。-This procedure achieved PCM30 frame synchronization and detection step, using verilog programming, includes the project file.
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Size: 45056 |
Author: chenjian |
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Description: SDH开销的接收处理，要求：
1， A1和A2字节为帧头指示字节，A1为“11110110”，A2为“00101000”，连续3个A1字节后跟连续3个A2字节表示SDH一帧的开始。要求自行设计状态机，从连续传输的SDH字节流中找出帧头。
2， E2字节为勤务话通道开销，用于公务联络语音通道，其比特串行速率为64KHz(8*8K=64)。要求从SDH字节流中，提取E2字节，并按照64K速率分别串行输出E2码流及时钟，其中64K时钟要求基本均匀。（输出端口包括串行数据和64K串行时钟）
-Receiving SDH overhead processing requirements: 1, A1 and A2 bytes instruction byte header, A1 is " 11110110" , A2 is " 00101000" , for three consecutive A1 bytes followed by three A2 bytes of an SDH the beginning of the frame. Asked to design a state machine, from the continuous stream of bytes in the SDH transmission header to find out. 2, E2-byte path overhead for the service, then, for the public to contact voice channels, the bit-serial rate 64KHz (8* 8K = 64). SDH byte stream request from the extraction E2 bytes, and the serial output in accordance with rates of E2 64K stream and clock, which clock requires 64K basic uniform. (Including the serial data output port and 64K serial clock)
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Size: 2048 |
Author: 刘镇宇 |
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