Search - Verilog m

[Other] m序列

Description: Verilog编写的M序列发生器，希望能对大家带来帮助。 -Verilog prepared by the M-sequence generator, we hope to bring help.
Platform: | Size: 4913 | Author: 张林 | Hits:

[VHDL-FPGA-Verilog] 一篇用VHDL实现快速傅立叶变换的论文

Description: 一篇用VHDL实现快速傅立叶变换的论文，包括原理分析和代码实现，印度圣雄甘地大学M.A.学院提供-VHDL with a Fast Fourier Transform papers, including the principle of analysis and implementation of the code, the Mahatma Gandhi Institute of the University of Marat
Platform: | Size: 62464 | Author: | Hits:

[VHDL-FPGA-Verilog] pseudorandom

Description: 伪随机m序列产生的VHDL语言程序- program in VHDL language for generating pseudo-random m sequence
Platform: | Size: 2048 | Author: 张庆辉 | Hits:

[Communication] 伪随机序列

Description: 线形反馈移位寄存器（LFSR)是数字系统中一个重要的结构，本程序可以自动产生AHDL,VHDL,Verilog的源代码及电路原理图。程序可以运行在win98/2000/NT平台-linear feedback shift register (LFSR) digital system is an important structure, the process can be automatically generated AHDL, VHDL, Verilog source code and circuit schematics. Procedures can run on platforms win98/2000/NT
Platform: | Size: 162816 | Author: 夏沫 | Hits:

[Crack Hack] MD5(verilog)

Description: MD5算法的verilog实现，同时包含有testbench。-Verilog of MD5 algorithm is realized, includes testbench at the same time .
Platform: | Size: 4096 | Author: 张雷 | Hits:

[Other] m序列

Description: Verilog编写的M序列发生器，希望能对大家带来帮助。 -Verilog prepared by the M-sequence generator, we hope to bring help.
Platform: | Size: 5120 | Author: 张林 | Hits:

[Windows CE] DDSFPGA_cylone

Description: dds设计，花了一个星期做的,verilog写的，可生成多种波形，频率范围可上M,性能不错。-dds design, spent a week doing, verilog written, multiple waveform generation, frequency range available on the M, good performance.
Platform: | Size: 637952 | Author: 苏纳 | Hits:

[VHDL-FPGA-Verilog] magnitude

Description: Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm. -Verilog HDL : For a vector magnitude (a, b), the magnitude representation is the following : A common approach to implementing thes e arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonome tric functions of sine, cosine, magn itude, and phase using an iterative process. It i 's made up of a series of micro-rotations of the v ector by a set of predetermined cons tants, which are powers of two. Using binary ar praxiology metic, this algorithm essentially replaces m ultipliers with shift and add operations. In a Stratix
Platform: | Size: 12288 | Author: 郝晋 | Hits:

[VHDL-FPGA-Verilog] VerilogHDL

Description: 《设计与验证Verilog HDL》光盘内容-err
Platform: | Size: 1003520 | Author: jzhupo | Hits:

[RFID] qencode

Description: LDPC中的q进制编码算法，已经通过，由m语言也有c语言-Q in M-ary LDPC coding algorithm, has been passed by the m language also has c language
Platform: | Size: 88064 | Author: 王果 | Hits:

[Software Engineering] MAC

Description: 本文首先讨论了以太网介质访问控制MAC的功能和工作过程。接着介绍了以太网MAC芯片的一种设计方案，对MAC的功能进行了逻辑划分。据此可以用Verilog HDL或VHDL来加以描述，并进一步用FPCA或ASIC来加以实现，也可做成以太网MAC核.-err
Platform: | Size: 181248 | Author: charles | Hits:

[VHDL-FPGA-Verilog] alu

Description: 4bit ALU（运算逻辑单元）的设计给出了此次设计alu的输入输出结构及相应的位数。其中C0是一位的进位输入，A和B分别是4位的数据输入，S0、S1、M分别为一位的功能选择输入信号；Cout是一位的进位输出，F是4为的运算结果输出。-4bit ALU (arithmetic logic unit) design is given in the design of alu input and output structure and the corresponding median. C0 which is a binary input of, A and B are four data entry, S0, S1, M, respectively, as a function of choice of the input signal Cout of a binary output, F is 4 for computing the results of output.
Platform: | Size: 1024 | Author: chenyi | Hits:

[VHDL-FPGA-Verilog] pn

Description: 用Verilog语言生成7位的小m序列，产生pn码-Verilog language used to generate seven small m sequence code generated pn
Platform: | Size: 2048 | Author: 楚鹤 | Hits:

[VHDL-FPGA-Verilog] signalprocess_fft_VHDL

Description: 一篇用VHDL实现快速傅立叶变换的论文，包括原理分析和代码实现，印度圣雄甘地大学M.A.学院提供，同时包含使用手册，做FFT很好的-VHDL with a fast Fourier transform papers, including the principle of analysis and code, India Mahatma Gandhi Institute of the University of MA, at the same time contains the user manual, so good FFT
Platform: | Size: 391168 | Author: 费尔德 | Hits:

[mpeg mp3] mp3decoder

Description: mp3 解码的verilog代码，通过仿真综合及验证，能够播放所有的.mp3文件。压缩包包括所有的verilog源码以及详细的文档。-mp3 decoding Verilog code, the adoption of an integrated simulation and verification, can all play. mp3 file. Compressed packet including all the Verilog source code and detailed documentation.
Platform: | Size: 169984 | Author: 刘名 | Hits:

[Other] Verilog

Description: verilog的简要教程基本逻辑门，例如a n d、o r和n a n d等都内置在语言中。 • 用户定义原语（ U D P）创建的灵活性。用户定义的原语既可以是组合逻辑原语，也可以是时序逻辑原语。 • 开关级基本结构模型，例如p m o s 和n m o s等也被内置在语言中。-Verilog tutorial briefly the basic logic gates, such as and, or and NAND are built in the language. • user-defined primitives (UDP) to create flexibility. User-defined primitives are the combinational logic can be the original language may also be a temporal logic primitives. • The basic structure of switch-level models, such as PMOS and NMOS are also being built in the language.
Platform: | Size: 4169728 | Author: 阿春 | Hits:

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[Other] m序列

[VHDL-FPGA-Verilog] 一篇用VHDL实现快速傅立叶变换的论文

[VHDL-FPGA-Verilog] pseudorandom

[Communication] 伪随机序列

[Crack Hack] MD5(verilog)

[Other] m序列

[Windows CE] DDSFPGA_cylone

[VHDL-FPGA-Verilog] magnitude

[VHDL-FPGA-Verilog] VerilogHDL

[RFID] qencode

[Software Engineering] MAC

[VHDL-FPGA-Verilog] alu

[VHDL-FPGA-Verilog] pn

[VHDL-FPGA-Verilog] signalprocess_fft_VHDL

[mpeg mp3] mp3decoder

[Other] Verilog

[VHDL-FPGA-Verilog] LIP1732CORE_system_mbus_arbiter

[VHDL-FPGA-Verilog] Verilog----m

[VHDL-FPGA-Verilog] m_sequence

[VHDL-FPGA-Verilog] m-test

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