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[VHDL-FPGA-Verilog] State.Machine

Description: State.Machine.Coding.Styles.for.Synthesis（状态机，英文,VHDL）-State.Machine.Coding.Styles.for.Synthesis (FSM, English, VHDL)
Platform: | Size: 123904 | Author: | Hits:

[VHDL-FPGA-Verilog] Verilog-statemachine

Description: 利用Verilog编程实现状态机的例子。很不错的。-use Verilog Programming state machine example. Very good.
Platform: | Size: 183296 | Author: 张厂 | Hits:

[Other] statemachine11.2

Description: 推荐下载,verilog状态机实例.体现了流水线思想的应用 -recommend downloading Verilog state machine example. Pipeline reflects the thinking of the application
Platform: | Size: 2048 | Author: 陶玉辉 | Hits:

[VHDL-FPGA-Verilog] washmachine

Description: 在MAXPULS II环境下，采用Verilog开发的自动洗衣机的控制程序,在MAXPULS下可以直接通过编译-in MAXPULS II environment, using Verilog development of the automatic washing machine control procedures, the MAXPULS can be directly through the compiler
Platform: | Size: 282624 | Author: 余远恒 | Hits:

[VHDL-FPGA-Verilog] xcv

Description: verilog编写的状态机检测00100序列. 实现 input:...011000010010000... output:...000000000100100... 并且 用测试模块来验证状态是否正确工作-verilog prepared by the state machine detected 00,100 sequences. Achieve input : ... ... 011000010010000 output : 000000000100100 ... ... and test module used to verify the state is working
Platform: | Size: 6144 | Author: 陆磊 | Hits:

[Other Embeded program] trafficLight-verilog

Description: 交通灯状态机的实现，用verilog HDL编程，Xilinx ISE 6仿真，在实际电路中得到验证．-traffic lights to achieve the state machine, with verilog HDL programming, Xilinx ISE 6 simulation, the actual circuit have been tested.
Platform: | Size: 1532928 | Author: 王越 | Hits:

[VHDL-FPGA-Verilog] 9.7_DIRIVER_control

Description: 基于Verilog-HDL的硬件电路的实现 9.7 步进电机的控制 　　9.7.1 步进电机驱动的逻辑符号 　　9.7.2 步进电机驱动的时序图 　　9.7.3 步进电机驱动的逻辑框图 　　9.7.4 计数模块的设计与实现 　　9.7.5 译码模块的设计与实现 　　9.7.6 步进电机驱动的Verilog-HDL描述　 　　9.7.7 编译指令-"宏替换`define"的使用方法 　　9.7.8 编译指令-"时间尺度`timescale"的使用方法 　　9.7.9 系统任务-"$finish"的使用方法 　　9.7.10 步进电机驱动的硬件实现 -based on Verilog-HDL hardware Circuit of 9.7 Stepper Motor Control 9.7 .1 stepper motor-driven logic symbols 9.7.2 stepper motor driven map the chronology-- Step 9.7.3 Machine-driven logic diagram 9.7.4 Counting Module Design and Implementation 9.7.5 decoding module design and Implementation 9.7.6 stepper motor driven Verilog-HDL Compiler means locale 9.7.7 Description Order- "macro substitution` define "the use 9.7.8 compiler directives-" The time scale `tim escale "use 9.7.9 system tasks-" $ finish "to use 9.7.10 stepper motor drive hardware
Platform: | Size: 2048 | Author: 宁宁 | Hits:

[Other] VerilogandVHDL

Description: Verilog and VHDL状态机设计，英文pdf格式 State machine design techniques for Verilog and VHDL Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding presented. Different methodologies will be compared using real-world examples.-Verilog and VHDL state machine design, English pdf format State machine design techniques for Ve rilog and VHDL Abstract : Designing a synchronous finite state Another w ay of organizing a state machine (FSM) is a commo n task for a digital logic only one logic block as shown in engineer. This paper will discuss a var iety of issues regarding FSM design using Synop sys Design Compiler. Verilog and VHDL coding st yles will be 2.0 Basic HDL coding presented. Dif ferent methodologies will be compared using're al-world examples.
Platform: | Size: 113664 | Author: mingming | Hits:

[VHDL-FPGA-Verilog] maxbijiao

Description: 在quaters下写的比较数的大小输出，verilog语言写的，具有状态机和存储器-Written in the quaters of the size of the comparator output, verilog language written with the state machine and memory
Platform: | Size: 30720 | Author: 王金栓 | Hits:

[Other] how_to_write_state_machine

Description: 介绍写状态机的好资料，大家下载啊 基于VERILOG的-Write state machine introduce good information, everyone download ah Verilog based on the
Platform: | Size: 294912 | Author: 段小康 | Hits:

[Software Engineering] Veilogbook

Description: 第一章 数字信号处理、计算、程序、算法和硬线逻辑的基本概念 第二章 Verilog HDL设计方法概述 第三章 Verilog HDL的基本语法 第四章 不同抽象级别的Verilog HDL模型 第五章 基本运算逻辑和它们的Verilog HDL模型 第六章 运算和数据流动控制逻辑 第七章 有限状态机和可综合风格的Verilog HDL-The first chapter of digital signal processing, computing, procedures, algorithms and hard-wired logic of the basic concepts of Chapter II Verilog HDL design methods outlined in Chapter III of the basic Verilog HDL syntax in Chapter IV of different abstraction levels of Verilog HDL model of Chapter V of the basic arithmetic logic and Verilog HDL model of their Chapter VI computing and data flow control logic of Chapter VII of the finite state machine and an integrated style of Verilog HDL
Platform: | Size: 1079296 | Author: 碗筷 | Hits:

[VHDL-FPGA-Verilog] i2c_slave

Description: I2c中通信的从机发送和接收信息的Verilog程序测试模块，用Modelsim仿真通过-I2C communication from machine to send and receive information Verilog module test procedures, using ModelSim simulation through
Platform: | Size: 5120 | Author: Tomersun | Hits:

[VHDL-FPGA-Verilog] TOUBIYINLIAO

Description: verilog HDL自动投币售饮料机程序，分一元和五毛，有找零功能。-verilog HDL automatic coin machine beverage sale procedures, sub-one dollar and fifty cents, and give change function.
Platform: | Size: 1024 | Author: 王义 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 一个简单状态机的.v文件，含testbench-A simple state machine. V file containing Testbench
Platform: | Size: 1024 | Author: QU YIFAN | Hits:

[Software Engineering] synopsis_FSM_coding

Description: synopsis的有限状态机编码方法的文档。 针对synopsis的综合环境，根据其综合工具的特点说明安全可靠、速度适合的FSM编码风格。 FSM coding style under synopsis. Used for verilog or vhdl designer. Good study data for ASIC newhand.-synopsis of the finite state machine coding documents. Synopsis for the integrated environment, in accordance with its characteristics of integrated tools that secure and reliable, speed appropriate FSM coding style. FSM coding style under synopsis. Used for verilog or vhdl designer. Good study data for ASIC newhand.
Platform: | Size: 119808 | Author: road | Hits:

[VHDL-FPGA-Verilog] 4bit_buma_adder

Description: Verilog作业 ：自己写的源码输入，补码输出的，由状态机控制的四位加法器，为保证时序，加法器模块为超前近位加法器，包含测试台，通过 Modelsim 、Synplify仿真。-Verilog operation: the source code to write their own input, complementary code output by the state machine to control the four adder, in order to ensure timing, adder module ahead of the last bit adder, including test bed, through the Modelsim, Synplify simulation.
Platform: | Size: 2048 | Author: wizard | Hits:

[Books] fsm

Description: 状态机设计.应用环境 verilog。让读者了解状态机的基本原理和应用。-State machine design. Application environment verilog. Allow readers to understand the basic principles of state machine and applications.
Platform: | Size: 66560 | Author: Mike | Hits:

[VHDL-FPGA-Verilog] traffic_controller

Description: it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].it is a state machine based code.-it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].it is a state machine based code.
Platform: | Size: 34816 | Author: yasir ateeq | Hits:

[VHDL-FPGA-Verilog] UART_for_FPGArar

Description: it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]-it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]
Platform: | Size: 5120 | Author: yasir ateeq | Hits:

[VHDL-FPGA-Verilog] softdrink

Description: 自动售货机实现，采用VERILOG语言编写源码，与大家分享，共大家参考-Vending machine implementation, the use of language VERILOG source to share with you a total of U.S. reference
Platform: | Size: 1024 | Author: wangdali | Hits:
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