Search - Verilog timer

[VHDL-FPGA-Verilog] stop_watch

Description: 采用Quartus2编写的电子秒表电路实现计时、暂停等功能-Quartus2 prepared using electronic stopwatch timer circuit, suspension and other functions
Platform: | Size: 349184 | Author: gz208 | Hits:

[VHDL-FPGA-Verilog] FPGA_jiaocheng_yu_shiyan

Description: 最重要的是七个从简单到复杂的实验，包括：基础实验一_FPGA_LED 基础实验二_seg7实验以及仿真基础实验三_SOPC_LED 基础实验四_Flash烧写基础实验五_定时器实验基础实验六_按键以及PIO口中断实验实验七_网卡使用，这些实验室用到了SOPC BUILDER 与NOIS ii ,使用Verilog 编写，有实验板和没有实验板的都可以用来学习。其次还包括： FPGA开发板各存储器之间的联系、多处理器文档、 USB_UART等文档，很好用的文档，您下了相信不会后悔！-The most important thing is seven from simple to complex experiments, including: the basis of the experimental basis for a _FPGA_LED experiment II _seg7 the basis of experiment and simulation experiments based on three experiments _SOPC_LED programmer _Flash the basis of four experiments of five experiments _ timer six experimental basis _ keys, as well as experimental experimental PIO interrupt I _ 7 card use, these laboratories used the SOPC BUILDER with NOIS ii, the use of Verilog to prepare, there are no experimental test panels and plates can be used to learn. The second also includes: FPGA development board of the links between memory, multi-processor documents, USB_UART such as documents, useful documents, you will not regret it a sure!
Platform: | Size: 6065152 | Author: yuezhiying_007 | Hits:

[VHDL-FPGA-Verilog] timer

Description: 淺顯易懂的學習verilog程式基礎範例以時鐘為示範-Learn easy to understand the basic Verilog code for an example of a clock model
Platform: | Size: 1024 | Author: 劉季泓 | Hits:

[VHDL-FPGA-Verilog] Timer

Description: ep2c5 实现定时器 verilog语言，quartus 2 仿真-verilog language to achieve ep2c5 timer, quartus 2 Simulation
Platform: | Size: 497664 | Author: lizhuodong | Hits:

[ActiveX/DCOM/ATL] pit_latest.tar

Description: Programmable Interval Timer: Overview Category :: Other Language :: Verilog Development status :: Beta WishBone Compliant :: Yes Phazes :: Design done, Specification done
Platform: | Size: 595968 | Author: Arun | Hits:

[SCM] timeclock

Description: 基于verilog的时钟定时器的硬件实现，可以实现时钟定时报时功能-Based on the verilog hardware timer clock can be achieved from time to time time clock function
Platform: | Size: 5120 | Author: 张利锋 | Hits:

[SCM] jishu60

Description: verilog实例，用verilog模块例化方式设计一个60S的定时器。-verilog example verilog modules were used to design a way of timer 60S.
Platform: | Size: 129024 | Author: liuxing | Hits:

[VHDL-FPGA-Verilog] timer

Description: 计时器的Verilog描述 CPU设计者可以借鉴 -Verilog decription of the timer in processors
Platform: | Size: 2048 | Author: Dee | Hits:

[.net] StopWatch

Description: 用C#写的跑表，用于学习Timer控件和C#下的stopwatch类，在VS.net 2005下运行通过.-Using C# to write the stopwatch for the study and Timer controls and C# under the stopwatch class, VS.net 2005 in the run through.
Platform: | Size: 38912 | Author: weixin | Hits:

[VHDL-FPGA-Verilog] watch_dog_rtl_source

Description: Watchdog timer verilog RTL code
Platform: | Size: 10240 | Author: Chris | Hits:

[VHDL-FPGA-Verilog] timer_rtl_source

Description: Timer verilog RTL code
Platform: | Size: 11264 | Author: Chris | Hits:

[Other] verilog

Description: verilog code for a microwave controller with clock output, clock time setting input, power control input+output, cooking timer setup, door open light, cooking complete buzzer output. Four push buttons provide following active low input signals: 1) KEY0 …………func_n 2) KEY1………….ten_sec_setup_n 3) KEY2………….one_min_setup_n 4) KEY3………….ten_min_setup_n Two high/low switches provide following input signals: 1) SW0……………reset_n 2) SW1……………open_door Three output signals to LEDs provide following functionality 1) LEDG0…………to_buzzer 2) LEDG1…………cook_enable 3) LEDG2…………to_lamp There are also four seven-bit signals going to 7-segemnt display 1) HEX0…………..to_sseg0 2) HEX1…………..to_sseg1 3) HEX2…………..to_sseg2 4) HEX3…………..to_sseg3-verilog code for a microwave controller with clock output, clock time setting input, power control input+output, cooking timer setup, door open light, cooking complete buzzer output. Four push buttons provide following active low input signals: 1) KEY0 …………func_n 2) KEY1………….ten_sec_setup_n 3) KEY2………….one_min_setup_n 4) KEY3………….ten_min_setup_n Two high/low switches provide following input signals: 1) SW0……………reset_n 2) SW1……………open_door Three output signals to LEDs provide following functionality 1) LEDG0…………to_buzzer 2) LEDG1…………cook_enable 3) LEDG2…………to_lamp There are also four seven-bit signals going to 7-segemnt display 1) HEX0…………..to_sseg0 2) HEX1…………..to_sseg1 3) HEX2…………..to_sseg2 4) HEX3…………..to_sseg3
Platform: | Size: 17408 | Author: ddr | Hits:

[VHDL-FPGA-Verilog] FPGA_Clk

Description: 基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。使用计时器的方式产生时钟波形。提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other modules. The use of the timer-generated clock waveform. To provide for the FPGA clock even sub-frequency, odd-numbered sub-frequency, pulse width is always functions.
Platform: | Size: 1466368 | Author: icemoon1987 | Hits:

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[VHDL-FPGA-Verilog] stop_watch

[VHDL-FPGA-Verilog] FPGA_jiaocheng_yu_shiyan

[VHDL-FPGA-Verilog] timer

[VHDL-FPGA-Verilog] Timer

[ActiveX/DCOM/ATL] pit_latest.tar

[SCM] timeclock

[SCM] jishu60

[VHDL-FPGA-Verilog] timer

[.net] StopWatch

[VHDL-FPGA-Verilog] watch_dog_rtl_source

[VHDL-FPGA-Verilog] timer_rtl_source

[Other] verilog

[VHDL-FPGA-Verilog] FPGA_Clk

[Other] gh_timer_8254_081608

[VHDL-FPGA-Verilog] mytime

[Static control] LIP1701CORE_system_watchdog

[VHDL-FPGA-Verilog] verilog

[VHDL-FPGA-Verilog] DW8051_core

[VHDL-FPGA-Verilog] time-counter

[VHDL-FPGA-Verilog] timer0

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