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[Other resource] adder

Description: 加法器（使用verilog编写的）,虽然简单，但是这也是学习verilog最基础的东西！希望大家一起学习！-The accumulator (uses the verilog compilation), although it is simple, but this also is studies most foundation of the verilog! Hopes everybody studies together!
Platform: | Size: 134368 | Author: 赵怀广 | Hits:

[VHDL-FPGA-Verilog] adder

Description: 加法器（使用verilog编写的）,虽然简单，但是这也是学习verilog最基础的东西！希望大家一起学习！-The accumulator (uses the verilog compilation), although it is simple, but this also is studies most foundation of the verilog! Hopes everybody studies together!
Platform: | Size: 134144 | Author: | Hits:

[VHDL-FPGA-Verilog] accumulator

Description: 实现累加器的verilog源码，广泛应用在通信电路设计中-The realization of accumulator Verilog source, widely used in communication circuit design
Platform: | Size: 1024 | Author: 文明 | Hits:

[VHDL-FPGA-Verilog] dds_easy

Description: 直接频率合成DDS模块的ise工程，可以直接下载，在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波，也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位，可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram，为节省储存空间仅需要储存1/4周期的数据。根据需要，可以重新修改数据，改变波形。-DDS direct frequency synthesizer module ，ise project, can be directly downloaded through the Spartan3/Spartan3E and tested successfully. The DDS module can generate two-channel sine wave of different frequency, or produce the same frequency arbitrary waveform phase difference of the phase shift. There is a 32-bit accumulator to generate 12 bit phase-precision 12-bit quantization precision of the sine wave. Cases the design of a Block Ram, in order to save storage space need to store only 1/4 cycle of data. Necessary, can modify data, change the waveform.
Platform: | Size: 471040 | Author: 郭先生 | Hits:

[Embeded Linux] 83390078DDS

Description: DDS的工作原理是以数控振荡器的方式产生频率、相位可控制的正弦波。电路一般包括基准时钟、频率累加器、相位累加器、幅度/相位转换电路、D/A转换器和低通滤波器（LPF）。频率累加器对输入信号进行累加运算，产生频率控制数据X（frequency data或相位步进量）。相位累加器由N位全加器和N位累加寄存器级联而成，对代表频率的2进制码进行累加运算，是典型的反馈电路，产生累加结果Y。幅度/相位转换电路实质上是一个波形寄存器，以供查表使用。读出的数据送入D/A转换器和低通滤波器。-DDS works the way we are digitally controlled oscillator frequency, phase controlled sine wave. Circuits generally include reference clock, frequency accumulator, phase accumulator, amplitude/phase converter circuit, D/A converter and low-pass filter (LPF). The frequency accumulator to accumulate the input signal operation to produce the frequency control data X (frequency data or phase stepping volume). From the N-bit phase accumulator and the N-bit full adder cascade accumulation register is made on behalf of the frequency of the two binary codes accumulation operation, is a typical feedback circuit, resulting in cumulative results of Y. Amplitude/phase converter circuit is essentially a waveform register for look-up table to use. Read out the data into the D/A converter and low pass filter.
Platform: | Size: 44032 | Author: 394177191 | Hits:

[Software Engineering] plugin-tut_timing_verilog_Lab2

Description: manual for time analysis and testing the critical path in verilog FPGA using Accumulator design
Platform: | Size: 389120 | Author: ahmed | Hits:

[Software Engineering] DDS1

Description: 直接数字频率合成器（Direct Digital synthesizer）是从相位概念出发直接合成所需波形的一种频率合成技术。一个直接数字频率合成器由相位累加器、加法器、波形存储ROM、D/A转换器和低通滤波器（LPF）构成-Direct digital frequency synthesizer (Direct Digital synthesizer) is the concept of direct synthesis from the requirements phase of a waveform synthesizer technology. A direct digital frequency synthesizer by the phase accumulator, adder, waveform storage ROM, D/A converter and low pass filter (LPF) constitute
Platform: | Size: 261120 | Author: wufeng | Hits:

[VHDL-FPGA-Verilog] xiangweileijiaqi

Description: 相位累加器，是数字频率合成器的重要组成部分。这是verilog代码。-Phase accumulator, digital frequency synthesizer is an important part. This is the verilog code.
Platform: | Size: 2048 | Author: yanzhengkuaile | Hits:

[Mathimatics-Numerical algorithms] MAC

Description: Multiplier/Accumulator written in Verilog
Platform: | Size: 384000 | Author: binh | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 本设计中应用硬件描述语言Verilog HDL描述相位累加器，相位调制器，正弦波、方波、三角波、心电波形四个独立的波形存储器，并描述频率控制、相位控字、幅度控制单元及波形切换等相关的功能单元。-Application of the design described in Verilog HDL hardware description language phase accumulator, phase modulator, sine, square, triangle wave, the four independent ECG waveform memory, and describe the frequency control, phase control word, control unit and the waveform amplitude switching and other related functional units.
Platform: | Size: 4096 | Author: kelly | Hits:

[VHDL-FPGA-Verilog] cla20_n

Description: Verilog 20 bit的累加器 采用流水香设计，用5级4bit的超前进位加法器-Verilog 20 bit accumulator using water in Hong design, with five 4bit the look-ahead adder
Platform: | Size: 1024 | Author: Yangyang | Hits:

[VHDL-FPGA-Verilog] robust_fir_latest.tar

Description: RobustVerilog generic FIR filter In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)). The filter can be built according to 3 different architectures, parallel, serial or something in the middle (named Nserial). The architecture is determined according to the MACNUM parameter (multiplayer-accumulator). The RobustVerilog top source file is fir.v. The command line calls it with an additional definition file named def_fir_top.txt The default definition file def_fir_top.txt generates 3 filters, 1 parallel, 1 serial and 1 Nserial. Changing the interconnect parameters should be made only in def_fir_top.txt in the src/base directory (changing multiplier number, filter order etc.).-RobustVerilog generic FIR filter In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)). The filter can be built according to 3 different architectures, parallel, serial or something in the middle (named Nserial). The architecture is determined according to the MACNUM parameter (multiplayer-accumulator). The RobustVerilog top source file is fir.v. The command line calls it with an additional definition file named def_fir_top.txt The default definition file def_fir_top.txt generates 3 filters, 1 parallel, 1 serial and 1 Nserial. Changing the interconnect parameters should be made only in def_fir_top.txt in the src/base directory (changing multiplier number, filter order etc.).
Platform: | Size: 6144 | Author: 尤恺元 | Hits:

[VHDL-FPGA-Verilog] acc32bit

Description: 本设计为32位数字相位累加器，门级描述的Verilog代码。其中，acc32bit.v为顶层文件，full_add1.v为一位全加器的门级描述模块，flop.v为触发器的门级描述模块。-The design for the 32-bit digital phase accumulator, gate-level description of the Verilog code. Which, acc32bit.v as top-level file, full_add1.v as a full adder gate-level description module, flop.v to trigger the gate-level description of the module.
Platform: | Size: 755712 | Author: 吴亮 | Hits:

[VHDL-FPGA-Verilog] mac

Description: verilog 实现乘累加器 源代码 以及测试代码 mac.v mac_tb.v-verilog Achieved by the source code and test code accumulator mac.v mac_tb.v
Platform: | Size: 1024 | Author: keyCSky | Hits:

[VHDL-FPGA-Verilog] MAC

Description: 在FPGA硬件上，使用verilog语言编写的一个乘累加器程序。-FPGA hardware, a multiply accumulator verilog language program.
Platform: | Size: 3072 | Author: 苏亭 | Hits:

[VHDL-FPGA-Verilog] Verilog-Accumulator

Description: the folder contains two files written by Verilog HDL. the first one is an implementation of an accumulator that takes serial data as an input, and its output will be an accumulated sum of each consecutive four input samples. the second file is a test bench for the first file to test its operation
Platform: | Size: 1024 | Author: sawsan | Hits:

[VHDL-FPGA-Verilog] Accumulator

Description: An 8-bit Accumulator with an adder module in Verilog HDL. You can change the bus width decoding the adder.
Platform: | Size: 6978560 | Author: Patrick Go | Hits:

[Other] accumulator

Description: 一个简单的加法器实现程序，已验证，使用的是Verilog HDL编写，适合初学者入门学习-A simple adder procedures, verified, using Verilog HDL prepared, for beginners to learn
Platform: | Size: 1024 | Author: 金贝贝 | Hits:

[VHDL-FPGA-Verilog] pipeline_add

Description: pipeline式累加器的verilog代码和testbench文件，已验证-pipeline type accumulator verilog testbench code and documents, verified
Platform: | Size: 4096 | Author: adfadf | Hits:

[Other] 用verilog编写的sigma-delta adc例子

Description: 累加器实现艾哈空间哈卡哈尽快啊哈卡哈卡快捷回复哈哈哈看(Accumulator implementation)
Platform: | Size: 4096 | Author: 西伯利亚牛 | Hits:
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