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[VHDL-FPGA-Verilog] adder

Description: 加法器（使用verilog编写的）,虽然简单，但是这也是学习verilog最基础的东西！希望大家一起学习！-The accumulator (uses the verilog compilation), although it is simple, but this also is studies most foundation of the verilog! Hopes everybody studies together!
Platform: | Size: 134144 | Author: | Hits:

[VHDL-FPGA-Verilog] adder16bit

Description: 16位高速加法器，采用verilog语言编写，已经成功仿真，能够运行-16 high-speed adder using Verilog language has been successful simulation can be run
Platform: | Size: 2048 | Author: modelsims | Hits:

[VHDL-FPGA-Verilog] CORDIC01

Description: CORDIC算法的硬件实现 用的verilog语言-CORDIC algorithm Hardware Implementation of the Verilog language
Platform: | Size: 221184 | Author: 李文文 | Hits:

[VHDL-FPGA-Verilog] adder_ahead8bit

Description: 本文件提供了用verilog HDL语言实现的8位超前进位加法器,充分说明了超前进位加法器和普通加法器之间的区别.-using verilog HDL achieve the eight-ahead adder, fully demonstrates the CLA for ordinary Adder and the distinction between.
Platform: | Size: 10240 | Author: 剑指眉梢 | Hits:

[VHDL-FPGA-Verilog] add_16_pipe

Description: 16位加法器的流水线计算,verilog代码，用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
Platform: | Size: 1024 | Author: qjyong | Hits:

[VHDL-FPGA-Verilog] LAC_adder16

Description: 十六位超前进位加法器，Verilog HDL-16-ahead adder, Verilog HDL
Platform: | Size: 214016 | Author: Li Yanwei | Hits:

[Embeded-SCM Develop] verilog.HDL.examples

Description: 许多非常有用的 Verilog 实例: ADC, FIFO, ADDER, MULTIPLIER 等-many very useful Verilog examples : ADC, FIFO, ADDER, MULTIPLIER etc.
Platform: | Size: 188416 | Author: 张驰 | Hits:

[VHDL-FPGA-Verilog] 89_full_adder

Description: full adder设计代码，verilog 语言描述，通过modelsim 仿真，quartus综合-full adder design code, verilog language to describe, through the ModelSim simulation, quartus integrated
Platform: | Size: 4096 | Author: shenyunfei | Hits:

[Other Embeded program] adder

Description: 基于ALTERA 公司cyclone系列FPGA的程序，verilog 实现加法器-ALTERA company based FPGA family of cyclone procedures, verilog adder realize
Platform: | Size: 209920 | Author: 陶德杰 | Hits:

[Other] add

Description: verilog加法器产生第0 位本位值和进位值产生第1 位本位值和进位值产生第2 位本位值和进位值-Adder Verilog generated the first 0-based values and binary values of the first value and a binary-based values of the first two binary-based value and the value of
Platform: | Size: 1024 | Author: 吕鹏 | Hits:

[VHDL-FPGA-Verilog] vhdlsource

Description: 用verilog hdl编写的一些例程，包括加法器/减法器等等，例子较多就不一一列举了-Verilog hdl prepared with some routines, including the adder/subtraction, etc., for example, more is not to enumerate the
Platform: | Size: 4096 | Author: 刘念洲 | Hits:

[VHDL-FPGA-Verilog] adder4

Description: verilog加法器,附加测试文件 可用modelsim 仿真实现-Verilog Adder, additional test file ModelSim simulation can be used to achieve
Platform: | Size: 5120 | Author: luminous | Hits:

[VHDL-FPGA-Verilog] Mars_EP1C6F_Fundermental_demo(Verilog)

Description: FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。-FPGA development board supporting Verilog HDL code. Chips for the Mars EP1C6F. Are the basic source experiment. Including the adder, subtraction, and multiplier, such as MUX.
Platform: | Size: 1244160 | Author: chenlu | Hits:

[VHDL-FPGA-Verilog] adder_fa4bit

Description: 4 bit full adder verilog code n test bench
Platform: | Size: 27648 | Author: M. Usman | Hits:

[VHDL-FPGA-Verilog] floating-point-adder

Description: verilog implementation of the floating point adder
Platform: | Size: 2048 | Author: ramtin | Hits:

[Software Engineering] 21-bit--leading-adder-Verilog

Description: 这是一个21位超前进位加法器的verilog程序。-21 bit leading adder verilog program.
Platform: | Size: 3072 | Author: 晨晨 | Hits:

[Software Engineering] 16-leading-adder-Verilog-program

Description: 这是一个16位超前进位加法器的Verilog程序。-This is a 16 bit leading adder verilog program.
Platform: | Size: 4096 | Author: 晨晨 | Hits:

[VHDL-FPGA-Verilog] 64Bit-Look-Ahead-Adder-Verilog-Code-with-Testbenc

Description: 64Bit Look Ahead Adder Verilog Code with Testbench
Platform: | Size: 2048 | Author: Anand | Hits:

[VHDL-FPGA-Verilog] 32-bit new csa adder verilog code

Description: 32-bit new carry select adder verilog code
Platform: | Size: 1236 | Author: gsrwork2017@gmail.com | Hits:

[VHDL-FPGA-Verilog] 32-bit carry select adder verilog code

Description: 32-bit conventional carry select adder verilog code
Platform: | Size: 745 | Author: gsrwork2017@gmail.com | Hits:
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