Search - altera i

[Other resource] AlteraIOTIME

Description: 应用文档，方便理解Altera i/O 输出时间，如何定义Tco,以及计算用户系统输出时间的方法！-application documents, facilitate understanding of Altera i / O output time, the definition of Tco. user and system output of the time!
Platform: | Size: 160773 | Author: dfd | Hits:

[Embeded-SCM Develop] perl561src

Description: Altera recommends the following system configuration: * Pentium II 400 with 512-MB system memory (faster systems give better software performance) * SVGA monitor * CD-ROM drive * One or more of the following I/O ports: - USB port (if using Windows XP or Windows 2000) for USB-Blaster(TM) or MasterBlaster(TM) communications cables, or APU programming unit - Parallel port for ByteBlasterMV(TM) or ByteBlaster(TM) II download cables - Serial port for MasterBlaster communications cable * TCP/IP networking protocol installed * Windows 2000, Windows NT 4.0 with Service Pack 3 or later, or Windows XP * Internet Explorer 5.0 or later Memory & Disk Space Requirements USB开发--Altera recommends the following system configuration:* Pentium II 400 with 512-MB system memory (faster systems give better software performance)* SVGA monitor* CD-ROM drive* One or more of the following I/O ports:- USB port (if using Windows XP or Windows 2000) for USB-Blaster(TM) or MasterBlaster(TM) communications cables, or APU programming unit- Parallel port for ByteBlasterMV(TM) or ByteBlaster(TM) II download cables- Serial port for MasterBlaster communications cable* TCP/IP networking protocol installed* Windows 2000, Windows NT 4.0 with Service Pack 3 or later, or Windows XP* Internet Explorer 5.0 or later Memory & Disk Space Requirements USB development
Platform: | Size: 7300096 | Author: 周元平 | Hits:

[VHDL-FPGA-Verilog] ByteBlasterii

Description: altera PLC/FPGA编程，ByteBlasterii原理，我按此原理做的板很好用。-ALTERA PLC/FPGA programming, ByteBlasterii principle, I do accordingly tenets of the plate is useful.
Platform: | Size: 202752 | Author: johndrf | Hits:

[Other Embeded program] lcd12

Description: 基于ＡＬＴＥＲＡ公司的ＤＥ２的ＬＣＤ显示程序，一起学习．非常好的资料，也非常难得．是我参加培训时所得-the DE2 LCD display program, learning together. Very good information, and they are extremely rare. I receive training
Platform: | Size: 5120 | Author: 唐老鸭 | Hits:

[Other] CycloneII_preliminary_fr

Description: ALtera FPGA CYCLONE系列的功耗计算工具，相信大家会用的着．-ALtera CYCLONE FPGA series of power calculation tool, I believe we would use to.
Platform: | Size: 96256 | Author: 喻袁洲 | Hits:

[Embeded-SCM Develop] SIN_fashengqi

Description: 2006altera大赛－基于软核Nios的宽谱正弦信号发生器设计：摘要：本设计运用了基于 Nios II 嵌入式处理器的 SOPC 技术。系统以 ALTERA公司的 Cyclone 系列 FPGA 为数字平台，将微处理器、总线、数字频率合成器、存储器和 I/O 接口等硬件设备集中在一片 FPGA 上，利用直接数字频率合成技术、数字调制技术实现所要求波形的产生，用 FPGA 中的 ROM 储存 DDS 所需的波形表，充分利用片上资源，提高了系统的精确度、稳定性和抗干扰性能。使用新的数字信号处理（DSP）技术，通过在 Nios 中软件编程解决不同的调制方式的实现和选择。系统频率实现 1Hz～20MHz 可调，步进达到了1Hz；完成了调幅、调频、二进制 PSK、二进制 ASK、二进制 FSK 调制和扫频输出的功能。 -2006altera race-based soft-core Nios wide spectrum of sinusoidal signal generator design : Abstract : The use of design-based Nios II embedded processor SOPC technology. Altera Corporation system to the Cyclone FPGA series of digital platform, microprocessor, bus, Digital Frequency Synthesizer, memory and I/O interface hardware concentrated in an FPGA, the use of direct digital frequency synthesis technology and digital modulation waveforms required to achieve the rise, Using FPGA ROM storage of the DDS waveform table, and make full use of on-chip resources, improve the system's accuracy, stability and robustness. Use of new digital signal processing (DSP) technology, Nios through software programming to solve different ways of achieving modulation and choice. Realize the system freq
Platform: | Size: 407552 | Author: 刘斐 | Hits:

[Embeded-SCM Develop] usb_jtag-20070215-1134

Description: USB JTAG 卡. 允许从主机USB口直接控制JTAG I/O 信号。 USB端与Altera USB-Blaster使用相同的协议。主机端与openwince, OpenOCD和Altera的软件兼容-USB JTAG card. From the mainframe to allow direct USB JTAG control I/O signals. USB terminal and Altera USB-Blaster use the same protocol. And the mainframe-openwince, OpenOCD and Altera software compatibility
Platform: | Size: 100352 | Author: 张森宁 | Hits:

[Software Engineering] AlteraIOTIME

Description: 应用文档，方便理解Altera i/O 输出时间，如何定义Tco,以及计算用户系统输出时间的方法！-application documents, facilitate understanding of Altera i/O output time, the definition of Tco. user and system output of the time!
Platform: | Size: 160768 | Author: dfd | Hits:

[Other] Modelsim-manual

Description: Modelsim中文教程,我看有这方面需要的朋友很多，但是站内的资源太少，和大家共享一下吧！-ModelSim Chinese Course, I do have friends in this area which needs a lot, but the station
Platform: | Size: 701440 | Author: pc4190 | Hits:

[VHDL-FPGA-Verilog] H1wQqGvI

Description: 详细介绍了ALTERA器件的IP CORE以及如何使用SDR SDRAM CONTROL-Described in detail ALTERA device IP CORE and how to use SDR SDRAM CONTROL
Platform: | Size: 777216 | Author: 黄辉辉 | Hits:

[VHDL-FPGA-Verilog] i2c_altera

Description: I2C总线控制器 altera公司提供VHDL实现代码-I2C bus controller altera companies realize VHDL code
Platform: | Size: 1598464 | Author: 张庆顺 | Hits:

[Software Engineering] Embedded_system_design_based_SOPC

Description: SOPC是Altera公司提出的一种灵活、高效的片上系统设计方案,它可以有选择地将处理器、存储器、I/O等系统设计需要的组件集成到一个PLD器件上。在SOPC设计中可方便地加入用户自定义逻辑。该文简要介绍了SOPC设计架构,然后通过一个实例,详细介绍了嵌入式系统中SOPC设计的实现方法和效果。-Altera Corporation SOPC is a flexible and efficient system-on-chip design, it can choose to have the processor, memory, I/O system design needs, such as components integrated into a PLD device. In SOPC design can be easily adding user-defined logic. The article briefly introduce the SOPC design framework, and then through an example of detailed SOPC embedded system design methods and results.
Platform: | Size: 173056 | Author: 郑宏超 | Hits:

[Other systems] OFDMpaprCodewithReport

Description: 课程作业，本人自编的OFDM峰均功率比抑制算法仿真(基于编码的方法和基于SLM的方法)，含详细的仿真报告-Coursework, I own the OFDM PAPR suppression algorithm simulation (based on the coding method and the method based on the SLM), containing a detailed simulation of the report
Platform: | Size: 183296 | Author: Liu | Hits:

[Other] LCD

Description: ALTERA上DE2平台，使用LCD模块，在LCD上显示字母字符。与已有程序相比，程序更加优化，代码更少。-ALTERA on DE2 platform, the use of LCD modules, LCD display in alphabetic characters. Compared with the existing procedures, procedures more optimized, less code.
Platform: | Size: 505856 | Author: 徐朝凯 | Hits:

[Other Embeded program] ALTERA

Description: 5款ALTERA FPGA开发板原理图合集。包括EP1C6Q240C6开发板原理图、Cyclone II EP2C20 原理图。希望对大家有用-5 ALTERA FPGA development board schematic diagram collection. Including EP1C6Q240C6 development board schematics, Cyclone II EP2C20 Schematic. I hope all of you a useful
Platform: | Size: 666624 | Author: 傅佩龙 | Hits:

[VHDL-FPGA-Verilog] Quartus2_VerilogRoutine

Description: 该文档是基于QUARTUS2_6.0的Verilog试验例程，其中附有工程源码，对于初学者是最好的例程！它是本人花费一年多自学后写的例程，以便初学者入门，里面附有很多图解，很详细！-The document is based on the Verilog test QUARTUS2_6.0 routines, including an engineering source code, for beginners is the best routine! It is, I spent more than a year after self-written routines in order to beginners entry, which accompanied by many diagrams, very detailed!
Platform: | Size: 4041728 | Author: 王斌 | Hits:

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