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[ARM-PowerPC-ColdFire-MIPS] appsnotes

Description: ARM体系结构各功能的application notes，官方版，部分功能提供代码。涵括 arm7 arm9 arm10-ARM architecture of the function of application notes, the official version, some features to provide the code. Covered arm7 arm9 arm10
Platform: | Size: 7871488 | Author: 周理忠 | Hits:

[VHDL-FPGA-Verilog] ApbTimer

Description: PowerFull Apb Timer Controller
Platform: | Size: 3072 | Author: esl | Hits:

[Static control] LIP1701CORE_system_watchdog

Description: System watchdog verilog code
Platform: | Size: 287744 | Author: jc | Hits:

[Linux-Unix] apb_timer

Description: Driver for Langwell APB timer based on Synopsis DesignWare.
Platform: | Size: 4096 | Author: nonraiqeng | Hits:

[Linux-Unix] apb_timer

Description: Driver for Langwell APB timer based on Synopsis DesignWare.
Platform: | Size: 5120 | Author: cqnohr | Hits:

[VHDL-FPGA-Verilog] timer

Description: Simple 32-bit timer realization with APB interface with support of interrupt generation and switching clock source.
Platform: | Size: 3072 | Author: scnn86 | Hits:

[Other] apb_timer

Description: Verilog code of timer for APB
Platform: | Size: 2048 | Author: Tan Nguyen | Hits:

[VHDL-FPGA-Verilog] 24_Timer

Description: 使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)
Platform: | Size: 1024 | Author: libus | Hits:

[VHDL-FPGA-Verilog] apb_timer.tar

Description: 是基于apb总线下的timer外设的rtl代码，主要包括apb_timer的master逻辑verilog，以及相应的开发文档，包括寄存器的描述，功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the description of registers, functional characteristics and so on.)
Platform: | Size: 67584 | Author: megmand | Hits:

[Other] APB_timer

Description: 设计一个挂载在 APB 总线上的计数器，按照 APB 的时序给计数器赋值，主 机通过地址对计数器进行配置，通过数据输入端口给计数器设置计数器最大值， 并通过数据输出端口输出计数器的计数值。该设计还设置了一个计数完成信号， 当计数器满足模式配置后的计数要求时，会将该信号拉高(A counter mounted on the APB bus is designed. The counter is assigned according to the sequence of APB The computer configures the counter through the address and sets the maximum value of the counter through the data input port, And output the count value of the counter through the data output port. The design also sets a count completion signal, When the counter meets the counting requirements after the mode configuration, the signal will be pulled high)
Platform: | Size: 312320 | Author: littbi | Hits:

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