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[Other resource] VHDL范例

Description: 最高优先级编码器 8位相等比较器 三人表决器（三种不同的描述方式） 加法器描述 8位总线收发器：74245 （注2） 地址译码（for m68008） 多路选择器（使用select语句） LED七段译码 多路选择器（使用if－else语句） 双2－4译码器：74139 多路选择器（使用when－else语句） 二进制到BCD码转换 多路选择器 （使用case语句） 二进制到格雷码转换 双向总线（注2） 汉明纠错吗译码器 三态总线（注2） 汉明纠错吗编码器 解复用器 -highest priority encoder, compared to eight for phase three of the vote (the description of three different ways) Adder Description eight bus Transceivers : 74,245 (Note 2) address decoder (for m68008) Multiple choice (use select statement) LED paragraph 107 of decoding multiple choice ( use if-else statements) 2-4 dual decoder : over 74,139 road choice (use when-else statements) of the binary conversion BCD multiple choice (use case statement) binary Gray code conversion to a two-way bus (Note 2)? Hamming error correction decoder three-state Bus (Note 2)? Hamming error correction encoder demultiplexer
Platform: | Size: 42884 | Author: kerty | Hits:

[SCM] VHDL范例

Description: 最高优先级编码器 8位相等比较器 三人表决器（三种不同的描述方式） 加法器描述 8位总线收发器：74245 （注2） 地址译码（for m68008） 多路选择器（使用select语句） LED七段译码 多路选择器（使用if－else语句） 双2－4译码器：74139 多路选择器（使用when－else语句） 二进制到BCD码转换 多路选择器 （使用case语句） 二进制到格雷码转换 双向总线（注2） 汉明纠错吗译码器 三态总线（注2） 汉明纠错吗编码器 解复用器 -highest priority encoder, compared to eight for phase three of the vote (the description of three different ways) Adder Description eight bus Transceivers : 74,245 (Note 2) address decoder (for m68008) Multiple choice (use select statement) LED paragraph 107 of decoding multiple choice ( use if-else statements) 2-4 dual decoder : over 74,139 road choice (use when-else statements) of the binary conversion BCD multiple choice (use case statement) binary Gray code conversion to a two-way bus (Note 2)? Hamming error correction decoder three-state Bus (Note 2)? Hamming error correction encoder demultiplexer
Platform: | Size: 43008 | Author: kerty | Hits:

[VHDL-FPGA-Verilog] VHDL_Development_Board_Sources

Description: 这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source code accompanied the development of the plate diagram, You hope to be a good help! which states : eight priority encoder, multipliers, multi-path selectors, BCD binary switch, adder, subtraction device, the simple state machine, four comparators, seven of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng, traffic lights, Digital Clock.
Platform: | Size: 4642816 | Author: Jawen | Hits:

[VHDL-FPGA-Verilog] Verilog_Development_Board_Sources

Description: 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code quite welcome, Now she will also be Verilog source contribution to everyone : eight priority encoder, multipliers, Multi-channel selector, binary to BCD, adder, subtraction device, the simple state machine, four comparators, 7 of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng. Traffic lights, digital clock
Platform: | Size: 3151872 | Author: Jawen | Hits:

[MPI] eecadd_4

Description: 此程序采用VHDL语言，完成四位二进制数的加法，并且输出是BCD码-VHDL language using this procedure to complete the four binary adder, and the output is BCD code
Platform: | Size: 41984 | Author: 韩善华 | Hits:

[MPI] add_16_bcd

Description: 此程序采用VHDL语言，完成在16位十六进制加法器的基础上将输出进行BCD码转换，实现输出是BCD码的16位二进制加法器-This procedure using VHDL language, completed in 16-bit hexadecimal adder based on output BCD code conversion, the realization of output is BCD code of 16 binary adder
Platform: | Size: 1024 | Author: 韩善华 | Hits:

[VHDL-FPGA-Verilog] add_32_bcd

Description: 此程序采用VHDL语言，完成在32位十六进制加法器的基础上将输出进行BCD码转换，实现输出是BCD码的32位二进制加法器-This procedure using VHDL language, completed in 32-bit hexadecimal adder based on output BCD code conversion, the realization of output is BCD code of 32 binary adder
Platform: | Size: 1024 | Author: 韩善华 | Hits:

[VHDL-FPGA-Verilog] work3CNT4BDECL7S

Description: 7段数码显示译码器设计7段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是二进制的，所以输出表达都是十六进制的，为了满足十六进制数的译码显示，最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器，输出信号LED7S的7位分别接数码管的7个段，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1；接有高电平的段发亮，于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as
Platform: | Size: 82944 | Author: lkiwood | Hits:

[Other] Trafficlight

Description: 系统设置一个两位BCD码倒计时计数器（计数脉冲1HZ），用于记录各状态持续时间； 因为各状态持续时间不一致，所以上述计数器应置入不同的预置数； 倒计时计数值输出至二个数码管显示； 程序共设置4个进程： ① 进程P1、P2和P3构成两个带有预置数功能的十进制计数器，其中P1和P3分别为个位和十位计数器，P2产生个位向十位的进位信号； ② P4是状态寄存器，控制状态的转换，并输出6盏交通灯的控制信号。-System to set up a two BCD code countdown counter (count pulse 1HZ), used to record the duration of each state because the duration of each state are inconsistent, so these counters should be placed in several different presets countdown of numerical output to two digital display procedures were set up four processes: ① process P1, P2 and P3 form two functions with a preset number of decimal counters, of which P1 and P3, respectively, for months, and 10-bit counters, P2 to generate a 10-bit The binary signal ② P4 is the status register, control the state of the conversion, and six output control signals of traffic lights.
Platform: | Size: 1024 | Author: kid | Hits:

[Other] binarytobcd

Description: 实现二进制到BCD的转换,相关算法可参考相关文档资料-convert binary number to BCD
Platform: | Size: 3072 | Author: CoCo | Hits:

[SCM] binarytobcd_arithmetic

Description: Binary to BCD arithmetic. 这东西真不错-Binary to BCD arithmetic. This is something really good
Platform: | Size: 3072 | Author: Reguse | Hits:

[VHDL-FPGA-Verilog] bin2bcd

Description: Binary to BCD converter
Platform: | Size: 1024 | Author: Natacho | Hits:

[VHDL-FPGA-Verilog] BIN_BCD

Description: 用硬件描述语音实现二进制数据转换成BCD数据-Using hardware description voice to achieve the binary data into BCD data
Platform: | Size: 620544 | Author: sleeeeeeep | Hits:

[VHDL-FPGA-Verilog] Binary_to_BCD_Converter

Description: General Binary-to-BCD Converter The linked code is a general binary-to-BCD Verilog module, and I have personally tested the code.
Platform: | Size: 25600 | Author: volkan | Hits:

[VHDL-FPGA-Verilog] HEX2BCD16

Description: 基于vhdl的二进制转BCD码的设计，已经经过调试，可直接使用-Vhdl based on binary code to BCD design, has been testing can be used directly
Platform: | Size: 1024 | Author: 郭帅 | Hits:

[VHDL-FPGA-Verilog] BCD

Description: 基于VHDL语言，实现二进制转换为BCD码。-Based on the VHDL language, to achieve a binary code is converted to BCD.
Platform: | Size: 3072 | Author: xiaokun | Hits:

[VHDL-FPGA-Verilog] 2-Decimal-BCD-Decoder

Description: 二-十进制BCD译码器，就是用VDHL编写的将二进制转化为十进制的BCD译码器-2- Decimal BCD Decoder, is to use VDHL written into the binary decimal BCD decoder
Platform: | Size: 1024 | Author: 易云箫 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 用VHDL语言实现的二进制到BCD码和格雷码的转换，程序通读性比较好。-VHDL language with the binary code and Gray code to BCD conversion, the program read through is better.
Platform: | Size: 1024 | Author: 周波 | Hits:

[Other] binary-to-bcd

Description: 二进制 转换成十进制 BCD码(加3移位法 底下还附带了BCD码转二进制码转化的VHDL程序 -Convert binary to decimal BCD code (plus 3 shift method also comes under the BCD to binary code conversion of the VHDL program
Platform: | Size: 11264 | Author: 王宝 | Hits:

[VHDL-FPGA-Verilog] baduanshumaguan

Description: 用VHDL语言设计并实现一电路，其功能是8个数码管分别显示数字0－7。首先是数码管0显示0，其他数码管不显示；然后是数码管1显示1，其他数码管不显示；依此类推，数码管7显示完后再显示数码管0，这样循环下去。（提示：数字0－7的循环可以使用8进制计数器对1Hz的时钟信号进行计数得到，计数器的输出送到BCD到七段数码管的译码器，由其驱动数码管显示相应的数字。）(Using VHDL language to design and implement a circuit, its function is 8 digital display digital 0-7. The first is the digital tube 0 display 0, other digital tube does not show; then digital tube 1 display 1, other digital tube does not show; and so on, digital tube 7 display after the display digital tube 0, so cycle. (hint: 0-7 cycles can be used 8 binary counter clock signal of the 1Hz count, the counter output to BCD to seven digital tube decoder, driven by digital display the corresponding number.))
Platform: | Size: 110592 | Author: 一个人丶 | Hits:
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