Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - bit divider

Search list

[VHDL-FPGA-Verilog] 200632146671689

Description: 基于vhdl在FPGA中实现高精度快速除法-based on the FPGA VHDL precision rapid division
Platform: | Size: 741376 | Author: lele | Hits:

[VHDL-FPGA-Verilog] div2

Description: 32位除法器 被除数和除数均为16位整数，16位小数 商为32位整数，16位小数 余数为16位整数，16位小数 Verilog HDL 代码-32 divider dividend and divisor are 16-bit integer, decimal 16 for the 32-bit integer, 16-bit decimal number more than 16 integer, 16-bit decimal Verilog HDL code
Platform: | Size: 1024 | Author: 李春阳 | Hits:

[VHDL-FPGA-Verilog] divider

Description: 此代码用于实现基2的SRT除法器设计，可以实现400MHz以上的32位定点无符号数除法器（除数、被除数和余数均由16位整数和16位小数组成，商由32位整数和16位小数构成,包括源代码和测试文件，可以直接仿真。-This code used to realize the base 2 SRT divider design, you can realize more than 400MHz unsigned 32-bit fixed-point divider number (divisor, dividend and the remainder by the 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 decimal places, including the source code and test files, you can direct simulation.
Platform: | Size: 2048 | Author: 朱秋玲 | Hits:

[VHDL-FPGA-Verilog] divider

Description: 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）-Based on the srt-2 algorithm, the use of Verilog to achieve 16-bit unsigned fixed-point divider number (divisor, dividend by 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 fractional composition, the remainder by 32 small array into)
Platform: | Size: 3072 | Author: 刘蒲霞 | Hits:

[VHDL-FPGA-Verilog] risc_cpu

Description: 8位risc cpu的编写，使用quartus软件对其进行写入，里面内置乘法器、除法器等模块-8-bit risc cpu the preparation, use the Quartus software to write, which built-in multiplier, divider modules
Platform: | Size: 814080 | Author: 瑞翔 | Hits:

[VHDL-FPGA-Verilog] 32divider

Description: 32位元2進位除法器 -32-bit binary divider 2
Platform: | Size: 2048 | Author: chen | Hits:

[VHDL-FPGA-Verilog] 32_16div

Description: 这是一个简单的除法器（32bit/16bit),采用移位相减法-This is a simple divider (32bit/16bit), using phase shift subtraction
Platform: | Size: 1024 | Author: 郭勇谅 | Hits:

[VHDL-FPGA-Verilog] div(FLP)

Description: 是Nios II處理器下客製化指令的一個32位元浮點數除法器，可將兩IEEE 754格式的值進行相除-Nios II processors are customized instruction under a 32-bit floating-point divider can be two format IEEE 754 value division
Platform: | Size: 18432 | Author: TTJ | Hits:

[ELanguage] 32bit

Description: multiplier and divider verilog codes
Platform: | Size: 6144 | Author: damasqas | Hits:

[VHDL-FPGA-Verilog] divide

Description: It is n-bit sequential divider in verilog language
Platform: | Size: 1024 | Author: Lisha | Hits:

[VHDL-FPGA-Verilog] divider

Description: 8位的除法器。用VHDL语言进行设计实现。-8-bit divider. With VHDL design languages.
Platform: | Size: 5120 | Author: 张怡萍 | Hits:

[VHDL-FPGA-Verilog] HG_chufaqi_clajiafaqi

Description: VHDL基-16位的无符号除法器，超前进位加法器可改位数。-VHDL-based-16 bit unsigned divider, CLA can be the median.
Platform: | Size: 2048 | Author: Huanggeng | Hits:

[VHDL-FPGA-Verilog] f_divider

Description: 16-bit frequency divider (32 MHz,16,8,...) based on altera fpga.
Platform: | Size: 455680 | Author: abu_faisul | Hits:

[VHDL-FPGA-Verilog] division1

Description: 基于vhdl/verilog的18位除法器程序。已经过仿真和综合。-Based on vhdl/verilog program for 18-bit divider. Has been simulation and synthesis.
Platform: | Size: 1024 | Author: 包鼎华 | Hits:

[VHDL-FPGA-Verilog] div_8

Description: 八位除法器 VHDL实现 八位除法器 VHDL实现-8-Bit divider 8-Bit divider 8-Bit divider
Platform: | Size: 1024 | Author: 郑书鑫 | Hits:

[VHDL-FPGA-Verilog] Chapter11-13

Description: 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter XI to the 13th chapter of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 5088256 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] 2

Description: 介绍一种软件实现分频器和32位计数器，采用可编程逻辑芯片，运用verilog语言设计出一种分频器和32位计数器 -Introduce a software implementation of divider and 32-bit counter, using programmable logic chips, using verilog language to design a divider and 32-bit counter
Platform: | Size: 158720 | Author: xxx | Hits:

[ARM-PowerPC-ColdFire-MIPS] 5956447divider

Description: 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）-Based on srt-2 algorithm, using verilog to achieve 16-bit fixed-point unsigned divider (divisor, dividend by 16-bit integer and 16-bit decimal form, business from the 32-bit integer and 16-bit fractional composition, I composed a few from the 32-bit decimal)
Platform: | Size: 3072 | Author: wfwef | Hits:

[VHDL-FPGA-Verilog] fpga_chufaqi

Description: 基于fpga的32位除法器的设计，开发环境vhdl-Fpga-based 32-bit divider design, development environment vhdl
Platform: | Size: 265216 | Author: 贾恒龙 | Hits:

[VHDL-FPGA-Verilog] divider

Description: FPGA除法器的使用32位的，有商和余数-FPGA using 32-bit divider, there are the quotient and remainder
Platform: | Size: 1024 | Author: 余木 | Hits:
« 12 3 4 »

CodeBus www.codebus.net