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Description: verilog 编写的pic16c5x时钟模块-verilog prepared pic16c5x clock module
Platform: |
Size: 50914 |
Author: 谢迪 |
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Description: 用ＭＡＴＬＡＢ产生各种时钟信号，对于不同的模块产生适当的始终信号．
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Size: 2062124 |
Author: 杨文博 |
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Description: 用最少的CPLD资源,用Verilog在QuartusII7.1上实现的1280分频.
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Size: 612630 |
Author: pc repair |
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Description: 时钟发生器 clkgen 利用外来时钟信号clk 来生成一系列时钟信号clk1、fetch、alu_clk 送往CPU的其他部件
Platform: |
Size: 1224 |
Author: 王晨磊 |
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Description: verilog 编写的pic16c5x时钟模块-verilog prepared pic16c5x clock module
Platform: |
Size: 50176 |
Author: 谢迪 |
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Description: 用ＭＡＴＬＡＢ产生各种时钟信号，对于不同的模块产生适当的始终信号．
Platform: |
Size: 2062336 |
Author: 杨文博 |
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Description: 用最少的CPLD资源,用Verilog在QuartusII7.1上实现的1280分频.-CPLD with minimal resources, using Verilog in QuartusII7.1 to achieve the 1280 frequency.
Platform: |
Size: 612352 |
Author: pc repair |
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Description: 时钟发生器 clkgen 利用外来时钟信号clk 来生成一系列时钟信号clk1、fetch、alu_clk 送往CPU的其他部件-Clock Generator clkgen use of external clock signal clk to generate a series of clock signal clk1, fetch, alu_clk sent to other parts of the CPU
Platform: |
Size: 1024 |
Author: 王晨磊 |
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Description: 用Verilog写的一个简单的IIs控制器，分为clkgen时钟分频模块和transcon传输控制模块。其中transcon模块主要部分为一个有限状态机实现的满足IIS标准的输出。
另附一个简单的Testcase以及得到的波形。-Develop an iis controller with verilog hdl. The key parts of iis were departed in two. One is clkgen.v which generate the clk and sync singnal we want and the transcon.v is used for contrl the FSM of the iis.
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Size: 605184 |
Author: hgdai |
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Description: 移位寄存器实现分频，避免大量使用分频代码-Frequency shift registers
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Size: 1024 |
Author: dong_tsinghua |
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Description: AXI clkgen driver for Linux.
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Size: 2048 |
Author: hinugin |
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Description: C-code for register scope clkgen.
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Size: 1024 |
Author: houdinmong |
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Description: Register r bootsel, scope clkgen.
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Size: 3072 |
Author: juiwdtr |
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Description: Binding for a ST pll clock driver.
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Size: 1024 |
Author: pinhutang |
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Description: Binding for a ST multiplexed clock driver.
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Size: 2048 |
Author: kangkingdt |
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Description: Binding for a type of STMicroelectronics clock crossbar (VCC).
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Size: 16384 |
Author: gfbanlan |
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Description: This binding uses the common clock binding.
Platform: |
Size: 1024 |
Author: ktqvkr |
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Description: clkgen-mux.c: ST GEN-MUX Clock driver.
Platform: |
Size: 4096 |
Author: jgxkfi |
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Description: AXI clkgen driver for Linux v2.13.6.
Platform: |
Size: 3072 |
Author: gingkwpang |
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Description: Linux MegaRAID driver for SAS based RAID controllers.
Platform: |
Size: 10240 |
Author: junbjbs |
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