Search - clkgen

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[Other resource] clkgen DL : 0: verilog 编写的pic16c5x时钟模块-verilog prepared pic16c5x clock module
Date : 2008-10-13 Size : 49.72kb User : 谢迪
[Other resource] clkgen DL : 0: 用ＭＡＴＬＡＢ产生各种时钟信号，对于不同的模块产生适当的始终信号．
Date : 2008-10-13 Size : 1.97mb User : 杨文博
[Other resource] clkgen DL : 0: 用最少的CPLD资源,用Verilog在QuartusII7.1上实现的1280分频.
Date : 2008-10-13 Size : 598.27kb User : pc repair
[WEB Code] clk DL : 0: 时钟发生器 clkgen 利用外来时钟信号clk 来生成一系列时钟信号clk1、fetch、alu_clk 送往CPU的其他部件
Date : 2008-10-13 Size : 1.2kb User : 王晨磊
[Other Embeded program] clkgen DL : 0: verilog 编写的pic16c5x时钟模块-verilog prepared pic16c5x clock module
Date : 2025-07-04 Size : 49kb User : 谢迪
[matlab] clkgen DL : 0: 用ＭＡＴＬＡＢ产生各种时钟信号，对于不同的模块产生适当的始终信号．
Date : 2025-07-04 Size : 1.97mb User : 杨文博
[Other Embeded program] clkgen DL : 0: 用最少的CPLD资源,用Verilog在QuartusII7.1上实现的1280分频.-CPLD with minimal resources, using Verilog in QuartusII7.1 to achieve the 1280 frequency.
Date : 2025-07-04 Size : 598kb User : pc repair
[Documents] clk DL : 0: 时钟发生器 clkgen 利用外来时钟信号clk 来生成一系列时钟信号clk1、fetch、alu_clk 送往CPU的其他部件-Clock Generator clkgen use of external clock signal clk to generate a series of clock signal clk1, fetch, alu_clk sent to other parts of the CPU
Date : 2025-07-04 Size : 1kb User : 王晨磊
[VHDL-FPGA-Verilog] iiscode DL : 0: 用Verilog写的一个简单的IIs控制器，分为clkgen时钟分频模块和transcon传输控制模块。其中transcon模块主要部分为一个有限状态机实现的满足IIS标准的输出。另附一个简单的Testcase以及得到的波形。-Develop an iis controller with verilog hdl. The key parts of iis were departed in two. One is clkgen.v which generate the clk and sync singnal we want and the transcon.v is used for contrl the FSM of the iis.
Date : 2025-07-04 Size : 591kb User : hgdai
[VHDL-FPGA-Verilog] clkgen DL : 0: 移位寄存器实现分频，避免大量使用分频代码-Frequency shift registers
Date : 2025-07-04 Size : 1kb User : dong_tsinghua
[Linux-Unix] clk-axi-clkgen DL : 0: AXI clkgen driver for Linux.
Date : 2025-07-04 Size : 2kb User : hinugin
[Linux-Unix] clkgen_defs DL : 0: C-code for register scope clkgen.
Date : 2025-07-04 Size : 1kb User : houdinmong
[Linux-Unix] extdev DL : 0: Register r bootsel, scope clkgen.
Date : 2025-07-04 Size : 3kb User : juiwdtr
[Linux-Unix] st-clkgen-pll DL : 0: Binding for a ST pll clock driver.
Date : 2025-07-04 Size : 1kb User : pinhutang
[Linux-Unix] st-clkgen-mux DL : 0: Binding for a ST multiplexed clock driver.
Date : 2025-07-04 Size : 2kb User : kangkingdt
[Linux-Unix] st-clkgen-vcc DL : 0: Binding for a type of STMicroelectronics clock crossbar (VCC).
Date : 2025-07-04 Size : 16kb User : gfbanlan
[Linux-Unix] axi-clkgen DL : 0: This binding uses the common clock binding.
Date : 2025-07-04 Size : 1kb User : ktqvkr
[Linux-Unix] clkgen-mux DL : 0: clkgen-mux.c: ST GEN-MUX Clock driver.
Date : 2025-07-04 Size : 4kb User : jgxkfi
[Linux-Unix] clk-axi-clkgen DL : 0: AXI clkgen driver for Linux v2.13.6.
Date : 2025-07-04 Size : 3kb User : gingkwpang
[Linux-Unix] st-clkgen DL : 0: Linux MegaRAID driver for SAS based RAID controllers.
Date : 2025-07-04 Size : 10kb User : junbjbs

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