Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - clock FPGA Verilog

Search list

[VHDL-FPGA-Verilog] codeofvhdl2006

Description: 【经典设计】VHDL源代码下载～～ 其中经典的设计有：【自动售货机】、【电子钟】、【红绿灯交通信号系统】、【步进电机定位控制系统】、【直流电机速度控制系统】、【计算器】、【点阵列LED显示控制系统】 基本数字逻辑设计有：【锁存器】、【多路选择器】、【三态门】、【双向输入|输出端口】、【内部（缓冲）信号】、【编码转换】、【加法器】、【编码器/译码器】、【4位乘法器】、【只读存储器】、【RSFF触发器】、【DFF触发器】、【JKFF触发器】、【计数器】、【分频器】、【寄存器】、【状态机】 - [ Classics design ] the VHDL source code downloads ~ ~ classics the design to include: [ Vending machine ], [ electron clock ], [ traffic light traffic signal system ], [ step of 杩涚數 machine localization control system ], [ direct current machine speed control system ], [ calculator ], [ array LED display control system ] the basic numeral logical design includes: [ Latch ], [ multichannel selector ], [ 涓夋
Platform: | Size: 44032 | Author: senkong | Hits:

[Static control] clock2001

Description: 时钟模块之一：二进制转BCD码verilog源代码FPGA advantage编程环境-clock module : BCD switch binary source code Verilog FPGA advantage programming environment
Platform: | Size: 1024 | Author: dandan | Hits:

[Other] FPGATiming

Description: FPGA时钟分析，包括门控时钟与时钟偏仪分析，逻辑设计时钟分析，毛刺分析．-FPGA clock analysis, including clock gating and clock partial analysis, logic design clock analysis, Burr analysis.
Platform: | Size: 630784 | Author: 罗辉 | Hits:

[VHDL-FPGA-Verilog] complex

Description: 时钟，信号灯verilog for FPGA -Clock signal verilog for FPGA
Platform: | Size: 3582976 | Author: zhaog gang | Hits:

[VHDL-FPGA-Verilog] multifunction_digital_clock_based_on_fpga

Description: 基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码，其功能主要有：时间设置，时间显示，跑表，分频，日期设置，日期显示等-FPGA-based multi-functional Digital Clock Design and Implementation of typhoons and rainstorms are detailed Verilog HDL source code, its functions include: time settings, time display, stopwatch, frequency, date setting, date display
Platform: | Size: 3293184 | Author: | Hits:

[VHDL-FPGA-Verilog] asynch_fifo

Description: FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输，已验证，直接可用-FPGA VERILOG using DCFIFO realize cross-clock domain data transfer, has been verified, directly available
Platform: | Size: 1028096 | Author: alison | Hits:

[VHDL-FPGA-Verilog] an_dcfifo_top_restored

Description: alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
Platform: | Size: 928768 | Author: alison | Hits:

[Embeded-SCM Develop] clock

Description: 用verilog实现的数字跑表，下载到FPGA开发板上验证通过。下载后从新分配引脚即可用。-Verilog implementation using digital stopwatch, download to FPGA development board to verify the adoption. After the download you can use the new distribution of pins.
Platform: | Size: 492544 | Author: lizhiqiang | Hits:

[VHDL-FPGA-Verilog] clock

Description: 多功能数字钟Verilog HDL的源码，能够整点报时，报整点数，设定任意时刻闹钟，低音高音两种频率。-Multi-function digital clock Verilog HDL source code, set the alarm clock at any time, bass treble two frequencies. It s for FPGA.
Platform: | Size: 984064 | Author: Stone Lei | Hits:

[VHDL-FPGA-Verilog] clock_divider

Description: clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc-clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc
Platform: | Size: 8192 | Author: sreejith | Hits:

[VHDL-FPGA-Verilog] clock

Description: 实现多功能电子表，含有闹铃，时间精确到毫秒-Achieve multi-functional electronic watch, with alarm, time, milliseconds
Platform: | Size: 2747392 | Author: 曹丽娜 | Hits:

[VHDL-FPGA-Verilog] verilogadc0809

Description: verilog adc0809控制器FPGA实现，编译通过，系统时钟分频，满足ADC时钟要求。-verilog adc0809 controller FPGA, compiler, system clock frequency to meet the requirements of ADC clock.
Platform: | Size: 344064 | Author: luo | Hits:

[VHDL-FPGA-Verilog] DCM

Description: xilinx SP605开发板的DCM模块验证程序，coreGen工具生成DCM核，由DCM完成时钟分频、倍频、移相等操作-xilinx SP605 development board DCM module validation program, coreGen tool to generate nuclear DCM, completed by the DCM clock divider, frequency, and shift operations equal
Platform: | Size: 2599936 | Author: wangyu | Hits:

[VHDL-FPGA-Verilog] cpu-kongzhi

Description: 1. 实现能够执行R型、LW、SW、BEQ以及J指令的单时钟控制器，使其能够支持基本的指令。 2. 用Verilog HDL实现单时钟CPU控制器，在ISE上进行波形仿真，并在FPGA上实现。-1. Implementations can perform R-type, LW, SW, BEQ, and J instruction every clock controller, to enable them to support the basic directives. 2 single-clock with Verilog HDL CPU controller, the ISE on the waveform simulation and FPGA implementation.
Platform: | Size: 1024 | Author: dino | Hits:

[VHDL-FPGA-Verilog] clock-design-verilog-Fpga

Description: verilog设计的计时表，数字电路设计，FPGA-using verilog design watch, digital circuit design, FPGA
Platform: | Size: 1525760 | Author: Nee | Hits:

[VHDL-FPGA-Verilog] FPGA-verilog-digital-clock

Description: FPGAverilog数字时钟,基于quartal ii 下的数字时钟电路程序-FPGA verilog digital clock
Platform: | Size: 2048 | Author: doudou | Hits:

[VHDL-FPGA-Verilog] digital-clock

Description: fpga verilog 2位数码管显示仿真及说明-fpga verilog 2 digit LED display and description of the simulation
Platform: | Size: 9216 | Author: 高路 | Hits:

[VHDL-FPGA-Verilog] Digital-clock

Description: 基于FPGA实现数码管数字时钟功能 使用芯片为EP2C8Q208C8N,使用数码管显示数字时钟，使用Verilog语言编程，本例子有工程文件、仿真、波形，经过测试可以使用。-Based on FPGA digital tube digital clock function uses chip EP2C8Q208C8N, use digital display digital clock, using Verilog language programming, the present examples are engineering documents, simulation, waveform, tested can be used.
Platform: | Size: 1220608 | Author: 陈怡然 | Hits:

[VHDL-FPGA-Verilog] Digital_clock

Description: 教程 基于FPGA的智能闹钟，控制NOKIA5110(Intelligent alarm clock based on FPGA, control N O K I A 5110)
Platform: | Size: 636928 | Author: Terence Zhao | Hits:

[VHDL-FPGA-Verilog] clock

Description: FPGA编程，用Verilog语言实现数字钟功能(The FPGA programming, the function for digital clock with Verilog language)
Platform: | Size: 1176576 | Author: 龚俊 | Hits:
« 12 3 4 5 6 »

CodeBus www.codebus.net