Search - clock generator

[Documents] clk

Description: 时钟发生器 clkgen 利用外来时钟信号clk 来生成一系列时钟信号clk1、fetch、alu_clk 送往CPU的其他部件-Clock Generator clkgen use of external clock signal clk to generate a series of clock signal clk1, fetch, alu_clk sent to other parts of the CPU
Platform: | Size: 1024 | Author: 王晨磊 | Hits:

[VHDL-FPGA-Verilog] VHDL-ROM4

Description: 基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), waveform generator control module and latch module 2. Waveform data storage module (ROM) custom data width of 8 , address width of 6, can store 64 points sinusoidal waveform data, waveform data are obtained using MATLAB. 3. To 50MHz clock as input.
Platform: | Size: 98304 | Author: 宫逢源 | Hits:

[Other] sheji2

Description: 一个秒表的硬件设计，学习数字电路中基本RS触发器、单稳态触发器、时钟发生器及计数、译码显示等单元电路的综合应用。-The hardware design of a stopwatch, learn basic digital circuit in the RS flip-flops, monostable multivibrator, the clock generator and counting, decoding display unit integrated circuit applications.
Platform: | Size: 131072 | Author: 周妮 | Hits:

[Speech/Voice recognition/combine] clk_en_gen

Description: 可靠的时钟产生器，采用同步设计，经过编译仿真，结果正确-Reliable clock generator, using synchronous design, compiled simulation, the results of the correct
Platform: | Size: 264192 | Author: 沈蝶 | Hits:

[VHDL-FPGA-Verilog] Clock_generator

Description: Verilog source code for a clock generator
Platform: | Size: 1024 | Author: austin | Hits:

[VHDL-FPGA-Verilog] FPGA_Clk

Description: 基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。使用计时器的方式产生时钟波形。提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other modules. The use of the timer-generated clock waveform. To provide for the FPGA clock even sub-frequency, odd-numbered sub-frequency, pulse width is always functions.
Platform: | Size: 1466368 | Author: icemoon1987 | Hits:

[VHDL-FPGA-Verilog] clock_generator

Description: clock generator verilog代码，供大家参考-clock generator verilog code for your reference
Platform: | Size: 163840 | Author: 袁科学 | Hits:

[Other] vhdl_code_files

Description: contains some self generated vhdl files. it includes a clock generator, CRc generator, pulse generator etc.
Platform: | Size: 10240 | Author: pri | Hits:

[VHDL-FPGA-Verilog] clock

Description: 时钟发生器，利用系统时钟获得需要的时钟信号-Clock generator, using the system clock to obtain the required clock signals
Platform: | Size: 1024 | Author: 清华 | Hits:

[VHDL-FPGA-Verilog] 5B6B-codec

Description: verilog hdl实现5B6B编译码（光纤通信线路码型），包含了时钟发生器模块，信号源模块，编码模块，译码模块，和检错模块，并通过modesim仿真验证。-verilog hdl achieve 5B6B encoding and decoding (code-based fiber-optic communication lines), contains a clock generator module, signal source modules, code modules, decoding module, and error detection module, and through modesim simulation.
Platform: | Size: 4096 | Author: 林海全 | Hits:

[SCM] clock-generator-based-on-TND8688

Description: 基于TND86/88教学系统。设计的电子时钟。设计思路：电子时钟主要由显示模块、对时模块和时钟运算模块三大部分组成。其中对时模块和时钟运算模块要对时、分、秒的数值进行操作，并且秒计算到60时，要自己清零并向分进1；分计算到60时，要自己清零并向时进1；时计算到24时，要清零。-clock generator based on TND8688
Platform: | Size: 2048 | Author: 谢芳芳 | Hits:

[SCM] clock-gennerater

Description: NEC单片机78K0R clock generator例程，PM+开发环境系统文件及C和ASM源程序-78K0R clock generator sample program
Platform: | Size: 167936 | Author: walker | Hits:

[VHDL-FPGA-Verilog] clock-divider

Description: clock generator vhdl code
Platform: | Size: 1024 | Author: sgma | Hits:

[VHDL-FPGA-Verilog] clock-generator

Description: 在集成电路设计中，时钟乃必备元素，但时钟产生器一般为模拟或者数模混合电路，在以数字电路为主的ASIC设计中，一般使用其模型来仿真。写一个时钟产生器模块。-In integrated circuit design, the clock is an essential element, but the clock generator is generally analog or mixed analog-digital circuits, digital circuits based ASIC design, the general use of the model to emulate. Write a clock generator module.
Platform: | Size: 123904 | Author: 彬 | Hits:

[Internet-Network] Clock-Generator-for-Cavium-Processors

Description: Clock Generator for Cavium Processors ICS8413S09I data sheet
Platform: | Size: 664576 | Author: Vasya | Hits:

[Software Engineering] Clock-Generator-ad9516

Description: Clock Generator ad9516
Platform: | Size: 1257472 | Author: alex | Hits:

[VHDL-FPGA-Verilog] clock

Description: Clock generator code in Verilog for Stop Watch
Platform: | Size: 1024 | Author: Uzair | Hits:

[DSP program] Application-19-Real-Time-Clock

Description: DSP编程，功能位实现一个实时的时钟发生器，开发软件为德州仪器的CCS-CCS DSP programming, functional position to implement a real-time clock generator, to develop software for the Texas Instruments
Platform: | Size: 584704 | Author: Lei | Hits:

[Goverment application] Clock-generator

Description: 采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置-.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings
Platform: | Size: 1024 | Author: hup123456 | Hits:

[VHDL-FPGA-Verilog] Clock generator

Description: A clock Generator in verilog
Platform: | Size: 1024 | Author: sadii | Hits:

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[Documents] clk

[VHDL-FPGA-Verilog] VHDL-ROM4

[Other] sheji2

[Speech/Voice recognition/combine] clk_en_gen

[VHDL-FPGA-Verilog] Clock_generator

[VHDL-FPGA-Verilog] FPGA_Clk

[VHDL-FPGA-Verilog] clock_generator

[Other] vhdl_code_files

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] 5B6B-codec

[SCM] clock-generator-based-on-TND8688

[SCM] clock-gennerater

[VHDL-FPGA-Verilog] clock-divider

[VHDL-FPGA-Verilog] clock-generator

[Internet-Network] Clock-Generator-for-Cavium-Processors

[Software Engineering] Clock-Generator-ad9516

[VHDL-FPGA-Verilog] clock

[DSP program] Application-19-Real-Time-Clock

[Goverment application] Clock-generator

[VHDL-FPGA-Verilog] Clock generator

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