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[Embeded-SCM Develop] verilog-clock

Description: 用verilog编写的多功能数字钟--Multifunctional digital clock written in verilog.
Platform: | Size: 1734 | Author: 李瑞 | Hits:

[Embeded-SCM Develop] verilog-clock

Description: 用verilog编写的多功能数字钟--Multifunctional digital clock written in verilog.
Platform: | Size: 1024 | Author: 李瑞 | Hits:

[VHDL-FPGA-Verilog] Verilog DHL数字钟

Description: 用Verilog DHL语言编写的一个数字钟程序,除了基本计数,还具有校时,闹钟功能-Verilog language used in the preparation of a digital clock procedures, in addition to the basic count, but also with school, an alarm clock
Platform: | Size: 2048 | Author: 谢树扬 | Hits:

[MPI] clock

Description: 用Verilog HDL写的数字时钟,已经在开发板上验证过的,绝对原创,使用数码管进行显示!-Written using Verilog HDL Digital Clock, has been verified in the development of on-board absolute originality, the use of digital tube display!
Platform: | Size: 2048 | Author: 吴俊泉 | Hits:

[VHDL-FPGA-Verilog] clock_design

Description: 数字钟的verilog代码，quartusII开发环境.-Digital Clock in Verilog code, quartusII development environment.
Platform: | Size: 414720 | Author: 屈开 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 自己编写的一个verilog时钟程序，在xilinx的ISE仿真通过-I have written a Verilog clock procedures, in Xilinx s ISE simulation through
Platform: | Size: 327680 | Author: lg | Hits:

[Program doc] clock

Description: verilog编写的时钟控制程序，在xilinx芯片上开发。具有案件防抖等考虑，-Verilog clock control procedures to prepare, in the Xilinx chip development. Anti-shake, such as with the case considered
Platform: | Size: 10240 | Author: 王忠 | Hits:

[VHDL-FPGA-Verilog] timer

Description: 淺顯易懂的學習verilog程式基礎範例以時鐘為示範-Learn easy to understand the basic Verilog code for an example of a clock model
Platform: | Size: 1024 | Author: 劉季泓 | Hits:

[2D Graphic] yavga

Description: This core is a simple and small VGA controller. * It drives vga monitors with an 800x600 resolution and 72Hz vertical refresh rate (50MHz pixel clock) * It displays chars on the screen (each char is 8x16 pixels) * It has a customizable charset (you can use a simple text editor in order to "visually" customize it) * It can display a color "waveform" * It can display a color grid and "cross cursor" -This core is a simple and small VGA controller. * It drives vga monitors with an 800x600 resolution and 72Hz vertical refresh rate (50MHz pixel clock) * It displays chars on the screen (each char is 8x16 pixels) * It has a customizable charset (you can use a simple text editor in order to "visually" customize it) * It can display a color "waveform" * It can display a color grid and "cross cursor"
Platform: | Size: 44032 | Author: sdroamt | Hits:

[VHDL-FPGA-Verilog] clock

Description: 用Verilog HDL编写的电子钟,实现一些简单功能,包括计时,调时-Written in Verilog HDL using electronic clock to achieve some simple functions, including timing, tone, when
Platform: | Size: 671744 | Author: liu | Hits:

[VHDL-FPGA-Verilog] Downloads

Description: clock divider in verilog for FPGA use
Platform: | Size: 1024 | Author: harini | Hits:

[VHDL-FPGA-Verilog] clock

Description: 这个程序是用verilog hdl语言编写，实现在数码管上显示时间，暂不支持调整-This program is written in verilog hdl to achieve in the digital tube display time, withhold support to the adjustment
Platform: | Size: 1024 | Author: Along | Hits:

[VHDL-FPGA-Verilog] clock

Description: verilog hdl代码 实现显示在数码管上显示时间，日期-verilog hdl code to achieve control in the digital display shows time, date. .
Platform: | Size: 2048 | Author: Along | Hits:

[VHDL-FPGA-Verilog] clock_divider

Description: clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc-clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc
Platform: | Size: 8192 | Author: sreejith | Hits:

[VHDL-FPGA-Verilog] quaddecoder_verilog_ise11.2_used_09042010

Description: Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descripted in the Constrained file quad.ucf. To use them, you need teh XC9536 and a clock source that s 4 times faster than the fastes signal that the incremental encoder can creates. IThe clock source frequency is uncritical. For manuel rotated incremental encoder like radio VFO oder other tuning knob, a simple TTL oscillator with about 1Mhz (i use 1.8432Mhz and tested 32768Khz) works brilliant. For very fast decoding, this core is not good enought because there are no Filter FlipFlops are programmed to suppress noises on the Channel A/B Lines.-Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descripted in the Constrained file quad.ucf. To use them, you need teh XC9536 and a clock source that s 4 times faster than the fastes signal that the incremental encoder can creates. IThe clock source frequency is uncritical. For manuel rotated incremental encoder like radio VFO oder other tuning knob, a simple TTL oscillator with about 1Mhz (i use 1.8432Mhz and tested 32768Khz) works brilliant. For very fast decoding, this core is not good enought because there are no Filter FlipFlops are programmed to suppress noises on the Channel A/B Lines.
Platform: | Size: 70656 | Author: JUPP | Hits:

[VHDL-FPGA-Verilog] my_clock

Description: 使用verilog HDL语言编写的时钟电路代码，能实现24小时电子钟的功能。-Using verilog HDL code written in the clock circuit can achieve 24-hour clock function.
Platform: | Size: 258048 | Author: 周朝 | Hits:

[VHDL-FPGA-Verilog] eda

Description: 利用ATMEL公司的QUETUSii软件编写的verilog语言程序，实现一个带复位、调整时间功能的电子钟，以数码管显示时间，调整时间时调整位闪烁-ATMEL Corporation QUETUSii using software written in verilog language program, the realization of a zone reset, adjust the time function of the electronic clock to digital display of time, adjusting time to adjust bit flash
Platform: | Size: 1591296 | Author: 秦玉龙 | Hits:

[VHDL-FPGA-Verilog] Multifunction-digital-clock

Description: 这是多功能数字钟的Verilog源程序，此程序已经编译通过，可以使用-This is a multi-functional digital clock in Verilog source code, this program has been compiled by, you can use
Platform: | Size: 493568 | Author: 莫然 | Hits:

[VHDL-FPGA-Verilog] Clock generator

Description: A clock Generator in verilog
Platform: | Size: 1024 | Author: sadii | Hits:

[VHDL-FPGA-Verilog] div_3

Description: 采用Verilog语言对时钟进行3分频，满足系统多时钟频率的要求(3 frequency division of clock in Verilog language to meet the requirement of multi clock frequency of the system)
Platform: | Size: 1126400 | Author: 天威浩荡 | Hits:
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