Description: 这是一个复数乘法器，相信对经常从事dsp信号处理的人士有帮助，该乘法器采用先进的dspbuilder进行建模，既简洁又实用。-This is a complex multiplier, believe that engaging in regular dsp signal processing to help those who have the multiplier dspbuilder the use of advanced modeling, both simple and practical. Platform: |
Size: 8192 |
Author:林盈 |
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Description: 复乘法器的FPGA实现， 希望对初学者有帮助
-Complex Multiplier FPGA to achieve, and they hope to help beginners Platform: |
Size: 1052672 |
Author:shirley |
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Description: 基于实数的二进制表示法，把CDF(Cohen，Daubechies and Feauveau)9／7双正交小波基的提升系数化为二进制，采用简单的移位一加操作代替结构复杂的浮点乘法器，从而实现了JPEG2000中9／7离散小波变换的定点计算．相对于浮点计算法，移位一加操作最大的优点是计算简单，特别易于超大规模集成电路实现，因而使硬件实时处理图像信号成为可能．实验仿真结果表明：在低压缩比的情况下，用移位一加操作重构的图像，其峰值信噪比(PSNR)只比浮点法低0．10 dB，当压缩比增大时，其PSNR值略好于浮点法．
关键词： 离散小波变换；定点计算；浮点计算法；提升；移位一加操作-Based on the real number of binary notation, the CDF (Cohen, Daubechies and Feauveau) 9/7 Biorthogonal wavelet enhancement factor into the binary, using a simple shift operation in place of one plus the complex structure of floating-point multiplier, in order to achieve the JPEG2000 9/7 discrete wavelet transform the fixed-point calculation. Compared with the floating-point calculations, shift operation of one plus the biggest advantages is the calculation is simple, especially vulnerable to the realization of ultra-large-scale integrated circuits, making real-time image processing hardware signal possible Platform: |
Size: 226304 |
Author:H Simon |
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Description: 潘明海 刘英哲 于维双 (论文)
中文摘要：
本文讨论了一种可在FPGA上实现的FFT结构。该结构采用基于流水线结构和快速并行乘法器的蝶形处理器。乘法器采用改进的Booth算法，简化了部分积符号扩展，使用Wallace树结构和4-2压缩器对部分积归约。以8点复点FFT为实例设计相应的控制电路。使用VHDL语言完成设计，并综合到FPGA中。从综合的结果看该结构可在XC4025E-2上以52MHz的时钟高速运行。在此基础上易于扩展为大点数FFT运算结构。
-Pan Minghai Liuying Zhe Yu-dimensional pairs (thesis) Chinese Abstract: This paper discusses an FPGA can be implemented on the structure of the FFT. The architecture based on pipeline architecture and fast parallel multiplier butterfly processor. Multiplier using modified Booth algorithm simplifying the partial product sign extension, use the Wallace tree and 4-2 compressor for partial product reduction. 8-point complex-point FFT as an example design of the corresponding control circuit. To complete the design using the VHDL language, and integrated into the FPGA. From the results of a comprehensive look at the structure can be XC4025E-2 with 52MHz clock on the high-speed operation. On this basis, easy to expand the structure for large point FFT operations. Platform: |
Size: 128000 |
Author:culun |
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Description: 用来实现两个复数的加减乘数
输出形式是实部，虚部分开
-Is used to achieve the addition and subtraction of two complex multiplier output form the real part, imaginary part of the open- Platform: |
Size: 2048 |
Author:llq |
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Description: fushutest用来实现两个复数的加减乘数,里面的代码需要自己填写-fushutest be used to achieve the addition and subtraction of two complex multiplier, which fill in the code that needs its own Platform: |
Size: 1024 |
Author:lc |
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Description: 图像的矩阵运算 用于图像像素的尺度变换，归一化；图像读取，阈值分割，矩阵的加减乘数运算，以及图像的读写；数据类型支持int，double，以及复数complex类型-Image matrix operations for image pixels scale transformation, normalization image reads, threshold segmentation, the multiplier matrix addition and subtraction operations, as well as images of reading and writing data type support int, double, and complex type of complex Platform: |
Size: 126976 |
Author:Jack |
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Description: 代码是一个复数乘法器，两个复数相乘，只用到了2个实数相乘，运算量少-Code is a complex multiplier, two complex multiplication, uses only real number multiplied by 2, operations less Platform: |
Size: 2048 |
Author:方波 |
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Description: 基于FPGA中OFDM中的帧检测，由于采用简化算法，采用较少的复数乘法器，易于硬件实现，且节省资源，采用verilog实现.-Frame detection based on FPGA for OFDM, a simplified algorithm, using less complex multiplier, easily implemented in hardware, and save resources, the SNR performance is slightly lower than the previous algorithm, but very practical. Platform: |
Size: 320512 |
Author: |
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Description: Abstract—Power is becoming a precious resource in
modern VLSI design, even more so than area. This paper
proposes a novel architecture for modular, scalable &reusable
hybrid constant co-efficient multiplier (KCM) circuit.
Comparison is made between of kcm and multiplier. The
implementation results show a significant improvement in
performance in terms of area, power & timing. In This paper,
we propose to design an 8-point FFT using kcm instead of
complex multiplier and multiplier. Here our goal is to
implement Radix-2 8-point FFT in hardware using hardware
language (verilog) here time constraint is measured with the
help of Xilinx FPGA (Field Programmable Gate Array).
Platform: |
Size: 560128 |
Author:Bahu |
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Description: 复数乘法器，利用ISE里的float IP核，实现了32位复数的乘法-Complex multiplier, using the ISE in the float IP core to achieve the 32 complex multiplications Platform: |
Size: 1024 |
Author:徐天伟 |
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Description: 4位的16点fft，ccmul为复数乘法器，bfproc为蝶形运算器，输出的结果为四位，每一级都要进行round操作。-4 16-point fft, ccmul for complex multiplier, bfproc for the butterfly operation, a result output is four, each stage should be carried out round operation. Platform: |
Size: 7168 |
Author:kove |
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Search - complex multiplier