Search - convolutional vhdl

Welcome！[Sign In] ！[Sign Up]！

Front-page it | Collect it | [中国-简体中文]

CodeBus

codebus.net

FAQ Fav

Location:

Search - convolutional vhdl

Search list

[VHDL-FPGA-Verilog] Convolutional encoding and Viterbi decoding with k

Description: 卷积码编码和维特比解码当K为7 时供大家参考Convolutional encoding and Viterbi decoding with k 7 rate 1 2 -convolutional coding and Viterbi decoding when K 7:00 for reference convolutional encoding and Viterbi decoding with k 1 2 7 rate
Platform: | Size: 253952 | Author: 周小川 | Hits:

[VHDL-FPGA-Verilog] conv_code

Description: 用VHDL实现卷积码编码，该码为（2.1.3）型卷积码。-using VHDL Convolutional coding, the code (2.1.3)- Convolutional Codes.
Platform: | Size: 1024 | Author: 武汉 | Hits:

[Communication-Mobile] Viterbi

Description: 卷积码（2，1，6），完整的工程文件，已经调试通过-Convolutional code (2,1,6), complete engineering documents have been debugging through
Platform: | Size: 47104 | Author: jishanyi | Hits:

[Communication] viterbidecoder

Description: 2，1，7卷积码的viterbi译码算法的FPGA实现，内容详细，而且附带源代码。-2,1,7 convolutional code of viterbi decoding algorithm realize the FPGA and detailed, but the source code attached.
Platform: | Size: 1665024 | Author: Wayne | Hits:

[VHDL-FPGA-Verilog] BCDconv

Description: BCD编码的Verilog HDL程序，能够实现BCD编码与卷积码。-BCD-coded Verilog HDL procedures, to achieve BCD encoding and convolutional codes.
Platform: | Size: 109568 | Author: 张明 | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: (2,1,9)卷积编解码器，译码部分采用Vitebi译码算法，设计使用Verilog HDL语言，在Modelsim平台下仿真通过-(2,1,9) convolutional codec, decoding part decoding algorithm used Vitebi design using Verilog HDL language simulation in ModelSim platform through
Platform: | Size: 10240 | Author: rxl | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: 卷积码编码及其Viterbi译码的实现-Convolutional code encoder and Viterbi decoding to achieve
Platform: | Size: 256000 | Author: mediative | Hits:

[ELanguage] acs

Description: 卷积码的解码所用到的加比选模块很有用可直接引用-Decoding convolutional codes by using the plus selection module can be directly useful to quote
Platform: | Size: 2048 | Author: 李俊 | Hits:

[VHDL-FPGA-Verilog] ViterbiDecodeK9R12HardDecision

Description: viterbi 硬判决译码，基本实现了（2，1，9）卷积码的硬判决译码，用modelsim RTL仿真通过-hard-decision viterbi decoding, the basic realization of the (2,1,9) convolutional codes hard decision decoding, using modelsim RTL simulation through
Platform: | Size: 12288 | Author: maojunling | Hits:

[Communication-Mobile] viter2

Description: verilog实现卷积码的译码，viterbi算法-verilog to achieve the decoding convolutional codes, viterbi algorithm
Platform: | Size: 8192 | Author: 张洪 | Hits:

[Other] interleaver

Description: This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
Platform: | Size: 2048 | Author: tomsontiger | Hits:

CodeBus www.codebus.net

“CodeBus” is the largest source code store in internet!

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[VHDL-FPGA-Verilog] Convolutional encoding and Viterbi decoding with k

[VHDL-FPGA-Verilog] conv_code

[Communication-Mobile] Viterbi

[Communication] viterbidecoder

[VHDL-FPGA-Verilog] BCDconv

[VHDL-FPGA-Verilog] viterbi

[VHDL-FPGA-Verilog] viterbi

[ELanguage] acs

[VHDL-FPGA-Verilog] ViterbiDecodeK9R12HardDecision

[Communication-Mobile] viter2

[Other] interleaver

[Communication-Mobile] fangzhen

[VHDL-FPGA-Verilog] viterbi

[VHDL-FPGA-Verilog] chengxu

[VHDL-FPGA-Verilog] Convolutionalencoder

[Communication] address_gen

[Communication] conv.vhd

[VHDL-FPGA-Verilog] project

[VHDL-FPGA-Verilog] viterbi

[Software Engineering] generate_trellis_rsc_c

CodeBus www.codebus.net