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[Other resource] MCU-counter

Description: 用verilog实现单片机计数器 用verilog实现单片机计数器-MCU with verilog counter with MCU counter verilog
Platform: | Size: 748106 | Author: ukh | Hits:

[VHDL-FPGA-Verilog] Verilog 编写的 计数器

Description: 用 verilog 编写的updown counter
Platform: | Size: 393581 | Author: sevenprince | Hits:

[Other Embeded program] countqi

Description: 计数器 同步异步预置数清零 verilog hdl 编写-Asynchrony preset counter reset the Verilog HDL few prepared
Platform: | Size: 271360 | Author: 周颖 | Hits:

[SCM] MCU-counter

Description: 用verilog实现单片机计数器 用verilog实现单片机计数器-MCU with verilog counter with MCU counter verilog
Platform: | Size: 747520 | Author: ukh | Hits:

[VHDL-FPGA-Verilog] 9.3_Pulse_Counter

Description: 基于Verilog-HDL的硬件电路的实现 9.3 脉冲计数与显示 　　9.3.1 脉冲计数器的工作原理 　　9.3.2 计数模块的设计与实现 　　9.3.3 parameter的使用方法 　　9.3.4 repeat循环语句的使用方法 　　9.3.5 系统函数$random的使用方法 　　9.3.6 脉冲计数器的Verilog-HDL描述 　　9.3.7 特定脉冲序列的发生 　　9.3.8 脉冲计数器的硬件实现 -based on Verilog-HDL hardware Circuit of 9.3 pulse count and showed 9.3 .1 pulse counter the principle 9.3.2 Counting Module Design and Implementation para 9.3.3 meter usage 9.3.4 repeat cycle statement on the use 9.3.5- EC $ random function of the use of pulse counter 9.3.6 Verilog-HDL depiction 9.3.7 to specific pulse sequences occurred pulse counter 9.3.8 Hardware Implementation
Platform: | Size: 4096 | Author: 宁宁 | Hits:

[VHDL-FPGA-Verilog] count

Description: 自己编制的计数器的verilog代码 希望能对大家有所帮助-Prepared their own counter Verilog code for all of us hope to be helpful
Platform: | Size: 1024 | Author: 舒畅 | Hits:

[VHDL-FPGA-Verilog] counter

Description: VHDL计数器的TestBench，适合初学者-VHDL counter TestBench, suitable for beginners
Platform: | Size: 1024 | Author: hbsun | Hits:

[VHDL-FPGA-Verilog] counter

Description: 计数器的VHDL设计，已经在FPGA上验证-VHDL counter design, has been tested in the FPGA
Platform: | Size: 1024 | Author: chen | Hits:

[MiddleWare] counter_4_bit

Description: 非常有参考价值的 计数器 源代码，用到了许多的编写程序的技巧，可以借鉴-Very useful counter source code, used in many programming skills, can learn from
Platform: | Size: 84992 | Author: 胡容华 | Hits:

[MiddleWare] counter

Description: 基于CPLD的计数器 实现光纤测距，包含与单片机的时序控制 Verilog 实现 通过仿真-CPLD-based counters realize optical ranging, single-chip microcomputer that contains timing control and realize the adoption of Verilog simulation
Platform: | Size: 2048 | Author: 强冰 | Hits:

[VHDL-FPGA-Verilog] counter

Description: verilog写的频率计程序的计数模块,-Verilog written procedures for counting frequency meter module,
Platform: | Size: 145408 | Author: chen | Hits:

[VHDL-FPGA-Verilog] Verilog--shiyanbaogao

Description: 有实验结果,用MOSIN6编写的,是Verilog HDL语言实现的. 练习三 利用条件语句实现计数分频时序电路 实验目的： 1. 掌握条件语句在简单时序模块设计中的使用； 2. 学习在Verilog模块中应用计数器； 3. 学习测试模块的编写、综合和不同层次的仿真。 练习四 阻塞赋值与非阻塞赋值的区别 实验目的： 1． 通过实验，掌握阻塞赋值与非阻塞赋值的概念和区别； 2． 了解阻塞赋值与非阻塞赋值的不同使用场合； 3． 学习测试模块的编写、综合和不同层次的仿真。 -The experimental results are used to prepare MOSIN6 is achieved Verilog HDL language. Practice the use of conditional statements to achieve the three sub-frequency timing circuit count experimental purposes: 1. Have conditional statements in the simple timing of the use of modular design 2. Learning modules in the Verilog Application of counter 3. to learn the preparation of the test module, integrated and different levels of simulation. Practicing the four blocking assignment with the distinction between non-blocking assignment experimental purposes: 1. Through experiments, hands blocking assignment with the concept of non-blocking assignment and distinction 2. Understanding of blocking and nonblocking assignment assignment using different occasions 3. Test the preparation of learning modules, integrated and different levels of simulation.
Platform: | Size: 15360 | Author: 盼盼 | Hits:

[VHDL-FPGA-Verilog] UpDownCounter

Description: an up down counter in verilog
Platform: | Size: 415744 | Author: ash | Hits:

[VHDL-FPGA-Verilog] UpDownCounter

Description: 8-Bit Up Down Counter Verilog Code
Platform: | Size: 306176 | Author: gunkaragoz | Hits:

[VHDL-FPGA-Verilog] counter

Description: 用Verilog HDL语言实现FPGA的频率等精度测量。（已经过验证）-Using Verilog HDL language, such as FPGA frequency measurement accuracy. (Has already been verified)
Platform: | Size: 2582528 | Author: double | Hits:

[VHDL-FPGA-Verilog] verilog-counter

Description: 利用Verilog实现的数字钟和汽车尾灯，有闹钟，报时，置数等多种功能-Verilog
Platform: | Size: 2048 | Author: xzd | Hits:

[VHDL-FPGA-Verilog] counter

Description: 关于FPGA实现的几种计数器的verilog源程序-FPGA implementation of several counter verilog source code
Platform: | Size: 2048 | Author: 王腾 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 文件包含了寄存器，移位寄存器，可能计数器，计数器等用VHDL实现的功能模块。-File contains the register, shift register, may counter, counter, implemented with the VHDL modules.
Platform: | Size: 4096 | Author: 朱向南 | Hits:

[VHDL-FPGA-Verilog] time-counter

Description: 基于verilog的计时器源代码，可以通过编译-Verilog source code based on the timer, you can compile
Platform: | Size: 2555904 | Author: 张迪 | Hits:

[VHDL-FPGA-Verilog] bcd counter

Description: Binary counter design in verilog
Platform: | Size: 176128 | Author: Armaghan | Hits:
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